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* i965: Fix assert conditions for src/dst x/y offsetsAnuj Phogat2016-03-211-3/+3
* i965/blorp: Make BlitFramebuffer() do sRGB encoding in ES 3.x.Kenneth Graunke2016-03-211-1/+4
* i965/blorp: Refactor sRGB encoding/decoding.Kenneth Graunke2016-03-214-11/+23
* i965: Stop XY clipping point and line primitives.Kenneth Graunke2016-03-181-1/+7
* i965: Scissor to the viewport when rendering points/lines.Kenneth Graunke2016-03-182-5/+8
* i965: Include the viewport in the scissor rectangle.Kenneth Graunke2016-03-181-4/+4
* i965: Introduce an is_drawing_lines() helper.Kenneth Graunke2016-03-181-0/+30
* i965: Move is_drawing_points to brw_state.h.Kenneth Graunke2016-03-182-24/+24
* i965: Fix gl_TessLevelOuter[] for isolines.Kenneth Graunke2016-03-182-6/+22
* i965: Decode non-normalized coordinates bit in SAMPLER_STATE.Kenneth Graunke2016-03-181-2/+3
* i965: Account for TES in is_drawing_points().Kenneth Graunke2016-03-181-1/+8
* nir: add a bit_size parameter to nir_ssa_dest_initConnor Abbott2016-03-171-2/+5
* nir: rename nir_const_value fields to include bitsize informationIago Toral Quiroga2016-03-176-63/+63
* nir: update opcode definitions for different bit sizesConnor Abbott2016-03-171-0/+18
* i965/nir: fix check to resolve booleans to work with sized nir_alu_typeSamuel Iglesias Gonsálvez2016-03-171-1/+1
* i965/nir: Lower nir compute shader shared variablesJordan Justen2016-03-173-0/+11
* i965: Skip execution size adjustment for instructions of width 4Iago Toral Quiroga2016-03-171-1/+13
* i965/vec4/gen6: fix exec_size for MOV with a width of 4 in generate_gs_ff_sync()Samuel Iglesias Gonsalvez2016-03-171-1/+3
* i965/vec4/gen6: fix exec_size for instructions with destination width of 4Samuel Iglesias Gonsalvez2016-03-171-0/+6
* i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs...Samuel Iglesias Gonsalvez2016-03-171-0/+3
* i965/gs/gen6: fix execsize for instructions with width of 4 in gen6_sol_progr...Samuel Iglesias Gonsalvez2016-03-171-1/+10
* i965: set correct execsize for MOVS with a width of 4 in brw_find_live_channelIago Toral Quiroga2016-03-171-0/+3
* i965/eu: set execution size for SEND message in brw_send_indirect_messageIago Toral Quiroga2016-03-171-0/+3
* i965/fs: Set exec size for gen7 pull const loadsIago Toral Quiroga2016-03-171-0/+1
* i965/eu: set correct execution size in brw_NOPIago Toral Quiroga2016-03-171-2/+3
* meta: Don't use integer handles for shaders or programs.Kenneth Graunke2016-03-163-33/+39
* meta: Use the _mesa_meta_compile_and_link_program helper more places.Kenneth Graunke2016-03-161-11/+3
* meta: Use ARB_explicit_attrib_location in the rest of the meta shaders.Kenneth Graunke2016-03-161-2/+2
* i965/fs: Restrict inequality that can only hold equal in saturate propagation.Francisco Jerez2016-03-141-1/+1
* i965/vec4: Consider removal of no-op MOVs as progress during register coalesce.Francisco Jerez2016-03-141-0/+1
* i965/fs: Add missing analysis invalidation in fixup_3src_null_dest().Francisco Jerez2016-03-141-0/+6
* i965/fs: Add missing analysis invalidation in opt_sampler_eot().Francisco Jerez2016-03-141-1/+4
* mesa: docs: Intel i965 hardware limits.Sarah Sharp2016-03-141-7/+48
* mesa: docs: i965: Use correct doxygen groupings syntaxSarah Sharp2016-03-141-2/+2
* i965: Remove useless IR self-destruct backend_shader method.Francisco Jerez2016-03-132-8/+0
* i965: Use foreach_in_list_reverse_safe() macro.Matt Turner2016-03-121-12/+2
* i965/chv: Display proper brandingBen Widawsky2016-03-113-5/+31
* i965/chv: Update lower min for CS threadsBen Widawsky2016-03-111-1/+1
* i965/chv: Check that compute threads are above thresholdBen Widawsky2016-03-112-0/+9
* i965/chv: Use kernel provided info for max_cs_threadsBen Widawsky2016-03-111-1/+8
* i965: Query and store GPU properties from kernelBen Widawsky2016-03-112-1/+31
* i965: Set a proper _BaseFormat for window system renderbuffers in ES.Kenneth Graunke2016-03-101-1/+1
* i915: limit extern "C" hack only for libdrm headersEmil Velikov2016-03-091-7/+6
* i965/hsw: Initialize SLM index in state registerJordan Justen2016-03-082-0/+23
* i965/compute: Skip SIMD8 generation if it can't be usedJordan Justen2016-03-081-8/+12
* i965/fs: Allow spilling for SIMD16 compute shadersJordan Justen2016-03-083-1/+14
* i965/fs/nir: "surface_access::" prefix not neededAlejandro Piñeiro2016-03-081-14/+10
* i965/vec4/nir: no need to use surface_access:: to call emit_untyped_atomicAlejandro Piñeiro2016-03-081-6/+5
* i965/vec4/nir: remove emit_untyped_surface_read and emit_untyped_atomic at br...Alejandro Piñeiro2016-03-083-75/+23
* i965/vec4: pass the correct src_sz to emit_send at emit_untyped_atomicAlejandro Piñeiro2016-03-081-1/+1
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