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path: root/src/mesa/drivers/dri
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* xmlconfig: add kernel_driver device attributeQiang Yu2018-08-176-6/+8
* i965: drop unused assignmentEric Engestrom2018-08-161-2/+0
* i965: do not emit empty surface stateErik Faye-Lund2018-08-151-0/+5
* intel/ppgtt: 4096 replaced by PAGE_SIZESergii Romantsov2018-08-151-6/+6
* intel/ppgtt: memory address alignmentSergii Romantsov2018-08-151-4/+3
* i965: Emitting 3DSTATE_SO_BUFFER of 0-size.Sergii Romantsov2018-08-151-4/+5
* i965/nir: Use the nir copy of shader_info to handle gl_PatchVerticesInNeil Roberts2018-08-131-1/+1
* i965: enable EXT_render_snormTapani Pälli2018-08-131-0/+1
* intel: Switch the order of the 2x MSAA sample positionsJason Ekstrand2018-08-112-9/+9
* meson: Build with Python 3Mathieu Bridon2018-08-101-1/+1
* i965: Only enable depth IZ signals if there's an actual depthbuffer.Kenneth Graunke2018-08-091-3/+8
* dri: Add param driCreateConfigs(mutable_render_buffer)Chad Versace2018-08-077-11/+17
* dri: Define DRI_MutableRenderBuffer extensionsChad Versace2018-08-073-0/+7
* i965: gen_shader_sha1() doesn't use the brw_contextEric Engestrom2018-08-071-4/+4
* mesa: add gl_renderbuffer::NumStorageSamplesMarek Olšák2018-08-041-0/+2
* intel/compiler: Add brw_get_compiler_config_value for disk cacheJordan Justen2018-08-011-1/+2
* i965: Disable shader cache with INTEL_DEBUG=shader_timeJordan Justen2018-08-011-0/+3
* i965: enable XFB and GeometryStreams for gen7+Alejandro Piñeiro2018-07-311-0/+2
* i965: Link XFB varyings for SPIR-V shadersNeil Roberts2018-07-311-0/+1
* i965: implement GL_MESA_framebuffer_flip_y [v3]Fritz Koenig2018-07-279-45/+43
* mesa: GL_MESA_framebuffer_flip_y extension [v4]Fritz Koenig2018-07-276-8/+31
* i965/icl: Disable binding table prefetchingTopi Pohjolainen2018-07-271-1/+13
* i965: Disable guardband clipping on SandyBridge for odd dimensionsvadym.shovkoplias2018-07-271-0/+11
* i965: Combine both gl_PatchVerticesIn lowering passes.Kenneth Graunke2018-07-262-51/+18
* i965: Expose EXT_base_instance extension in OpenGLES 3.0Sagar Ghuge2018-07-261-1/+1
* i965, anv: Use INTEL_DEBUG for disk_cache driver flagsJordan Justen2018-07-241-1/+2
* i965, anv: Add extra unused character in disk_cache renderer temp stringJordan Justen2018-07-241-2/+3
* python: Better iterate over dictionariesMathieu Bridon2018-07-241-2/+2
* intel/compiler: Account for built-in uniforms in analyze_ubo_rangesJason Ekstrand2018-07-235-5/+5
* i965/misc: Use depth/stencil surf's tiling on gen4-5Nanley Chery2018-07-191-1/+3
* intel/blorp: Take an explicit filter parameter in blorp_blitJason Ekstrand2018-07-181-2/+61
* i965: Sweep NIR after linking phase to free held memoryDanylo Piliaiev2018-07-181-0/+2
* intel/blorp: fix uninitialized variable warningCaio Marcelo de Oliveira Filho2018-07-181-3/+3
* i965/miptree: avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho2018-07-181-1/+2
* i965: batchbuffer: write correct canonical offset with softpinLionel Landwerlin2018-07-181-1/+2
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-6/+6
* i965/miptree: Allocate MS texture BOs as BUSYNanley Chery2018-07-131-2/+2
* i965/miptree: Inline make_separate_stencilNanley Chery2018-07-131-23/+6
* i965/miptree: Init r8stencil_needs_update to falseNanley Chery2018-07-131-3/+4
* i965/miptree: Refactor miptree_createNanley Chery2018-07-131-36/+12
* i965/miptree: Add and use mt_surf_usageNanley Chery2018-07-131-13/+25
* i965/miptree: Share alloc_flags in miptree_createNanley Chery2018-07-131-7/+4
* i965/miptree: Share the miptree format in miptree_createNanley Chery2018-07-131-15/+15
* i965/miptree: Share tiling_flags in miptree_createNanley Chery2018-07-131-8/+7
* i965/miptree: Delete MIPTREE_CREATE_LINEARNanley Chery2018-07-132-13/+3
* i965/miptree: Use make_surface in map_blitNanley Chery2018-07-131-6/+6
* i965/draw: Fix adding the stencil bo to the depth cacheNanley Chery2018-07-131-1/+1
* i965/draw: Set the r8stencil flag after drawingNanley Chery2018-07-131-1/+11
* i965/miptree: Set the r8stencil flag in map_depthstencilNanley Chery2018-07-131-1/+3
* i965: Set the r8stencil flag in miptree_finish_writeNanley Chery2018-07-134-17/+4
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