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* i965 gs: Move vue_map to brw_gs_compile.Paul Berry2011-12-202-3/+4
* i965 gen6+: Use 1-wide null operands for IF instructionsPaul Berry2011-12-201-4/+4
* i965: Advertise our vertex shader texture units.Kenneth Graunke2011-12-191-1/+1
* i965/vs: Implement EXT_texture_swizzle support for VS texturing.Kenneth Graunke2011-12-192-1/+52
* i965/vs: Add texture related data to brw_vs_prog_key.Kenneth Graunke2011-12-192-0/+11
* i965/fs: Only set brw_wm_prog_key data for samplers used by the WM.Kenneth Graunke2011-12-191-1/+3
* i965/fs: Factor out texturing related data from brw_wm_prog_key.Kenneth Graunke2011-12-197-115/+168
* i965/vs: Add support for texel offsets.Kenneth Graunke2011-12-193-2/+23
* i965/fs: Factor out texture offset bitfield computation.Kenneth Graunke2011-12-193-18/+26
* i965/vs: Implement vec4_visitor::visit(ir_texture *).Kenneth Graunke2011-12-191-7/+120
* i965/vs: Implement vec4_visitor::generate_tex().Kenneth Graunke2011-12-192-0/+110
* i965: Add missing SIMD4x2 sample_l_c message #defines.Kenneth Graunke2011-12-191-0/+1
* i965: Don't minify depth when setting up cube map miptrees on Gen4.Kenneth Graunke2011-12-191-1/+2
* i965: Add support for GL_ARB_depth_buffer_float under 3.0 override.Eric Anholt2011-12-194-1/+20
* i965: Add separate stencil/HiZ setup for MESA_FORMAT_Z32_FLOAT_X24S8.Eric Anholt2011-12-193-15/+20
* i965: Use the miptree format for texture surface format choice.Eric Anholt2011-12-192-2/+2
* i965: Add support for mapping Z32_FLOAT_X24S8 fake packed depth/stencil.Eric Anholt2011-12-191-5/+17
* intel: Stop creating the wrapped depth irb.Eric Anholt2011-12-192-111/+8
* i965: Properly demote the depth mt format for fake packed depth/stencil.Eric Anholt2011-12-194-3/+19
* intel: Reuse intel_miptree_match_image().Eric Anholt2011-12-191-9/+6
* intel: Stop creating the wrapped stencil irb.Eric Anholt2011-12-195-78/+67
* i965/vs: Add a new dst_reg constructor for file, number, type, and mask.Kenneth Graunke2011-12-181-0/+10
* i965/vs: Add vec4_instruction::is_tex() query.Kenneth Graunke2011-12-182-0/+11
* i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB.Kenneth Graunke2011-12-185-46/+48
* i965/fs: Don't swizzle the results of textureSize().Kenneth Graunke2011-12-181-0/+3
* mesa: implement DrawTransformFeedback from ARB_transform_feedback2Marek Olšák2011-12-153-7/+14
* i965: Drop separate stencil assertions in update_draw_buffer().Eric Anholt2011-12-141-16/+0
* intel: Simplify and touch up the FBO completeness test.Eric Anholt2011-12-141-18/+21
* intel: Remove another renderbuffer allocation path.Eric Anholt2011-12-141-8/+4
* intel: Make the separate stencil RB storage path match texture more.Eric Anholt2011-12-141-76/+52
* intel: Move S8 width/height alignment to miptree creation.Eric Anholt2011-12-143-55/+22
* intel: Drop check for wrapped_depth in RB mapping.Eric Anholt2011-12-141-1/+1
* intel: Fix uninitialized values in debug output for renderbuffer mapping.Eric Anholt2011-12-141-1/+1
* radeon: stop using _DepthBuffer, _StencilBuffer fieldsBrian Paul2011-12-132-9/+8
* nouveau: stop using _DepthBuffer, _StencilBuffer fieldsBrian Paul2011-12-136-13/+14
* mesa,intel: use _mesa_image_offset() for PBOsnobled2011-12-081-2/+3
* mesa/drivers: use new swrast renderbuffer functionsBrian Paul2011-12-087-35/+42
* mesa: rewrite accum buffer supportBrian Paul2011-12-081-1/+1
* i965 gen6: Implement pass-through GS for transform feedback.Paul Berry2011-12-076-46/+208
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-075-24/+59
* i965 gs: Clean up dodgy register re-use, at the cost of a few MOVs.Paul Berry2011-12-072-65/+111
* i965 gen6: Allocate URB space for GSPaul Berry2011-12-073-12/+63
* i965: Set the maximum number of GS URB entries on Sandybridge.Kenneth Graunke2011-12-071-0/+2
* i965: Only convert if/else to conditional adds prior to Gen6.Paul Berry2011-12-071-2/+28
* i965 gs: Remove unnecessary mapping of key->primitive.Paul Berry2011-12-072-16/+7
* i965: Set Ivybridge's is_array SURFACE_STATE bit.Kenneth Graunke2011-12-071-1/+2
* i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.Kenneth Graunke2011-12-071-0/+3
* intel: Update comment about how depth/stencil miptrees are handled.Eric Anholt2011-12-071-6/+18
* intel: Rely on miptree mapping for all renderbuffer maps.Eric Anholt2011-12-072-202/+21
* intel: Add support for LLC-cached reads of X-tiled miptrees using a blit.Eric Anholt2011-12-072-0/+83
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