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path: root/src/mesa/drivers/dri
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* driconfig: add a new engine name/version parameterLionel Landwerlin2019-09-156-8/+9
* dri: Use DRM_FORMAT_* instead of defining our own copy.Eric Anholt2019-09-112-46/+47
* intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WMAnuj Phogat2019-09-112-0/+9
* glsl/nir: Add and use a gl_nir_link() functionCaio Marcelo de Oliveira Filho2019-09-101-8/+4
* glsl/nir: Fill in the Parameters in NIR linkerCaio Marcelo de Oliveira Filho2019-09-101-1/+1
* mesa: Eliminate gl_config::rgbModeAdam Jackson2019-09-091-1/+0
* mesa: Eliminate gl_config::have{Accum,Depth,Stencil}BufferAdam Jackson2019-09-093-14/+6
* intel: Stop redirecting state cache to command streamer cache sectionKenneth Graunke2019-09-061-5/+0
* intel/dri: finish proper glthreadSergii Romantsov2019-09-051-1/+1
* i965: initialize bo_reuse when creating brw_bufmgrTapani Pälli2019-08-294-26/+15
* i965: Exit with error if gen12+ is detectedJordan Justen2019-08-281-0/+5
* intel/fs: Drop the gl_program from fs_visitorJason Ekstrand2019-08-252-2/+2
* i965: Silence brw_blorp uninitialized warningCaio Marcelo de Oliveira Filho2019-08-231-1/+1
* i965: honor scanout requirement from DRILionel Landwerlin2019-08-211-1/+3
* i965: Add handling for fp16 configsKevin Strasser2019-08-211-1/+24
* dri: Add fp16 formatsKevin Strasser2019-08-212-0/+22
* dri: Handle configs with floating point pixel dataKevin Strasser2019-08-211-0/+5
* dri: Add config attributes for color channel shiftKevin Strasser2019-08-211-19/+49
* i965: Add helper function for allowed config formatsKevin Strasser2019-08-211-31/+34
* nir: Add explicit signs to image min/max intrinsicsJason Ekstrand2019-08-211-2/+4
* i965: Enable OpenGL 4.6 for Gen8+Alejandro Piñeiro2019-08-212-2/+2
* i965: enable ARB_gl_spirv extension and ARB_spirv_extensions for gen7+Alejandro Piñeiro2019-08-211-0/+3
* i965/gen11: fix genX_bits.h include pathMauro Rossi2019-08-131-1/+1
* i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.Rafael Antognolli2019-08-122-0/+88
* intel/compiler: Fill a compiler statistics structJason Ekstrand2019-08-126-6/+7
* i965/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-125-6/+109
* i965/spirv: Lower shared memory laterCaio Marcelo de Oliveira Filho2019-08-101-0/+20
* i965: Use force_compat_profile driconf optionDanylo Piliaiev2019-08-102-2/+8
* i965: fix mem leak in error pathEric Engestrom2019-08-101-1/+3
* i965: don't use p_compiler.h typesLionel Landwerlin2019-08-091-1/+1
* meson: define ETIME to ETIMEDOUT if not presentGreg V2019-08-081-3/+0
* anv,i965,iris: deduplicate setting of total_sharedRhys Perry2019-08-081-2/+0
* i965: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3DDanylo Piliaiev2019-08-081-0/+21
* intel/perf: make perf context privateMark Janes2019-08-073-39/+27
* intel/perf: print debug informationMark Janes2019-08-071-25/+8
* intel/perf: expose method to create queryMark Janes2019-08-071-10/+3
* intel/perf: move initialization of pipeline statistics metrics to gen_perfMark Janes2019-08-071-93/+3
* intel/perf: move get_query_data into gen_perfMark Janes2019-08-072-399/+2
* intel/perf: move delete_query to gen_perfMark Janes2019-08-071-39/+1
* intel/perf: move is_query_ready to gen_perfMark Janes2019-08-071-133/+1
* intel/perf: move wait_query to perfMark Janes2019-08-071-38/+1
* intel/perf: create a vtable entry for bo_busyMark Janes2019-08-071-4/+5
* intel/perf: create a vtable entry for bo_wait_renderingMark Janes2019-08-071-1/+3
* intel/perf: create a vtable entry for batch_referencesMark Janes2019-08-071-6/+11
* intel/perf: refactor gen_perf_end_query into gen_perfMark Janes2019-08-071-45/+1
* intel/perf: refactor gen_perf_begin_query into gen_perfMark Janes2019-08-071-247/+1
* intel/perf: move perf-related state into gen_perf_contextMark Janes2019-08-071-49/+29
* intel/perf: create a vtable entries for buffer object map/unmapMark Janes2019-08-071-6/+12
* intel/perf: move client reference counts into perfMark Janes2019-08-071-36/+5
* intel/perf: move open_perf into perfMark Janes2019-08-071-48/+2
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