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* r300: fix register-negate branch merge regressionMaciej Cencora2009-04-203-39/+12
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* i965: use region width, height in brw_update_renderbuffer_surface()Brian Paul2009-04-181-2/+2
| | | | | Fixes a regression from commit 2c30fd84dfa052949a117c78d932b58c1f88b446 seen with DRI1.
* intel: #include polygon.h to silence warningBrian Paul2009-04-181-0/+1
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* intel: Handle ARB_vertex_buffer_object state in intel_clear_tris().Michel Dänzer2009-04-181-0/+5
| | | | Fixes gearsvbo app by Michael Clark.
* intel: make sure polygon mode is set properly in intel_clear_tris()Brian Paul2009-04-171-0/+2
| | | | Fixes progs/glsl/skinning.c demo.
* i915: fix broken indirect constant buffer readsBrian Paul2009-04-173-51/+40
| | | | | | | | The READ message's msg_control value can be 0 or 1 to indicate that the Oword should be read into the lower or upper half of the target register. It seems that the other half of the register gets clobbered though. So we read into two dest registers then use a MOV to combine the upper/lower halves.
* dri: __driUtilMessage(): not all messages are errorsBrian Paul2009-04-171-1/+1
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* i965: updated CURBE allocation codeBrian Paul2009-04-173-8/+15
| | | | | Now that we have real constant buffers, the demands on the CURBE are lessened. When we use real VS/WM constant buffers we only use the CURBE for clip planes.
* Merge branch 'register-negate'Brian Paul2009-04-1614-109/+93
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| * mesa: merge the prog_src_register::NegateBase and NegateAbs fieldsBrian Paul2009-04-1414-109/+93
| | | | | | | | | | | | There's really no need for two negation fields. This came from the GL_NV_fragment_program extension. The new, unified Negate bitfield applies after the absolute value step.
* | i915: Remove dead i830TexEnv and i915TexEnv.Eric Anholt2009-04-165-182/+0
| | | | | | | | | | These LOD bias updates are covered by the texture state uploads in *_texstate.c now.
* | intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.Eric Anholt2009-04-169-125/+346
| | | | | | | | | | | | Also enable them all regardless of screen bpp, as 32 bpp what I've been testing against, and haven't been able to detect any screen bpp-specific troubles with them.
* | i965: disable using immediate values for MOV instructionsBrian Paul2009-04-161-1/+3
| | | | | | | | | | | | For some reason, MOV instructions using immediate src values don't seem to work reliably on the GLSL path. Disable them for now (falling back to const buffer reads). This fixes a bunch of glean glsl1 failures.
* | i965: minor debug output changesBrian Paul2009-04-161-3/+3
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* | i965: const buffer debug code (disabled)Brian Paul2009-04-161-0/+12
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* | i965: implement relative addressing for VS constant buffer readsBrian Paul2009-04-163-59/+115
| | | | | | | | | | A scatter-read should be possible, but we're just using two READs for the time being.
* | i965: handle address reg in get_dst()Brian Paul2009-04-161-0/+4
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* | i965: fix const buffer temp register clobberingBrian Paul2009-04-161-7/+18
| | | | | | | | | | Calls to release_tmps() were causing the temps holding constants to get recycled.
* | intel: fix small compressed texture uploadRoland Scheidegger2009-04-161-4/+5
| | | | | | | | | | | | | | need to round up height for _mesa_copy_rect otherwise textures with height smaller than 4 won't get copied to the miptree at all Also fix up the confusing debug output (don't output unitialized values, and output if data is present and the compressed flag)
* | i965: Clean up output of WM SS state dump, and add format output.Eric Anholt2009-04-151-3/+17
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* | i915: Use DEBUG_WM (like 965) for printing the fragment program out.Eric Anholt2009-04-151-4/+2
| | | | | | | | | | This is nice when paired with INTEL_DEBUG=batch for debugging what's going out to the hardware.
* | i915: Add decode of dest buffer variables (destination format)Eric Anholt2009-04-151-0/+30
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* | intel: Fix segfault when doing SW mipmap generation with a PBO texture upload.Eric Anholt2009-04-151-3/+10
|/ | | | | Triggered in test-fbo from clutter since 37fb2d9b23eab5dbbb43a212c3475cb8016837d8.
* i965: fix VS constant buffer readsBrian Paul2009-04-143-35/+25
| | | | | | | This mostly came down to finding the right MRF incantation in the brw_dp_READ_4_vs() function. Note: this feature is still disabled (but getting close to done).
* DRI2: Don't fault on NULL DrawBufferIan Romanick2009-04-141-1/+1
| | | | | | | | | | It is possible for ctx->DrawBuffer to be NULL, so don't fault when that happens. This change is not being committed to master because it doesn't appear to be necessary there. Signed-off-by: Ian Romanick <[email protected]> Cherry picked from mesa_7_4_branch, commit 49e0c74ddd91900fc4effb6d305d56e0563b456d
* i965: checkpoint commit: VS constant buffersBrian Paul2009-04-1411-91/+477
| | | | | | Hook up a constant buffer, binding table, etc for the VS unit. This will allow using large constant buffers with vertex shaders. The new code is disabled at this time (use_const_buffer=FALSE).
* dri glx: Swap before checking for cliprects.Younes Manton2009-04-131-3/+3
| | | | | | | | | | | | We don't update drawables anymore unless they are completely uninitialized, so we need to swap even if we don't have cliprects yet, otherwise we never end up calling the driver's SwapBuffers(). The driver should update the drawable in its SwapBuffers() anyway. See 8e753d04045a82062ac34d3b2622eb9dba8af374, "dri glx: Fix dri_util::driBindContext" for the change that exposed it.
* i965: remove unused varBrian Paul2009-04-101-1/+0
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* i965: clean-up in prepare_wm_surfaces()Brian Paul2009-04-101-8/+4
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* mesa: reduce makefile outputBrian Paul2009-04-101-4/+5
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* i965: added null const_buffer pointer check in update_constant_buffer()Brian Paul2009-04-101-1/+1
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* intel: added screen->dri2.loader null pointer check in intel_flush()Brian Paul2009-04-101-1/+2
| | | | Fixes segfaults when rendering to front buffer.
* i965: re-org of some of the new constant buffer codeBrian Paul2009-04-094-48/+81
| | | | Plus, begin the new code for vertex shader const buffers.
* i965: new SURF_INDEX_ macrosBrian Paul2009-04-095-40/+49
| | | | | Used to map drawables, textures and constant buffers to surface binding table indexes.
* intel / DRI2: Accept fake front-buffer from loaderIan Romanick2009-04-091-0/+5
| | | | | | | | | Handle the loader returning a fake front-buffer. Since the driver never specifically requests a fake front-buffer, the driver assumes that it will never receive both a fake and a real front-buffer. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* intel / DRI2: Track and flush front-buffer renderingIan Romanick2009-04-093-0/+46
| | | | | | | | | | | Track two flags: whether or not front-buffer rendering is currently enabled and whether or not front-buffer rendering has been enabled since the last glFlush. If the second flag is set, the front-buffer is flushed via a loader call back. If the first flag is cleared, the second flag is cleared at this time. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: free shader's constant buffer in brwDeleteProgram()Brian Paul2009-04-091-0/+6
| | | | Fixes mem leak observed with texcombine test.
* i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()Brian Paul2009-04-081-1/+2
| | | | | | This fixes the random results that were seen when fetching a constant inside an IF/ELSE clause. Disabling the execution mask ensures that all the components of the register are written.
* i965: clean-ups, debug code in brw_wm_glsl.cBrian Paul2009-04-081-34/+15
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* i965: init current_const[i].index = -1Brian Paul2009-04-081-3/+4
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* i965: move the fetch_constants() call before setting conditional mod stateBrian Paul2009-04-081-4/+4
| | | | | | | | Before, the instruction's CondUpdate field was mistakenly effecting the constant-fetch operation. Fixes progs/glsl/bump.c demo. But there are some other issues related to condition flags and IF/ELSE that need investigation...
* intel: Avoid dri2 GetBuffers round-trips for internal Viewport calls.Eric Anholt2009-04-063-3/+10
| | | | | | This gets us the savings for driver-internal viewport calls that dd1c68f15123a889a3ce9d2afe724e272d163e32 was attempting, without relying on Xlib internals or clients handling X events.
* i965: Use GTT maps when available to upload vertex arrays and system VBOs.Eric Anholt2009-04-063-18/+55
| | | | | | | This speeds up OA on my GM45 by 21% (more than the original CPU cost of the upload path). We might still be able to squeeze a few more percent out by avoiding repeatedly mapping/unmapping buffers as we upload elements into them.
* intel: Clean up some a leftover from sedding of bufmgr context->screen move.Eric Anholt2009-04-061-3/+0
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* radeon: Expose a 32 bit RGBA fbconfig even when the screen depth is 16.Michel Dänzer2009-04-061-15/+20
| | | | | | | Otherwise current xserver / libGL no longer expose a 32 bit RGBA GLX visual, and compiz fails. Fixes http://bugs.freedesktop.org/show_bug.cgi?id=20479 .
* intel: #include texgetimage.hBrian Paul2009-04-031-0/+1
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* mesa: rename some gl_light fields to be clearerBrian Paul2009-04-033-12/+12
| | | | | EyeDirection -> SpotDirection _NormDirection -> _NormSpotDirection
* i965: remove unused varBrian Paul2009-04-031-1/+0
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* i965: more const buffer debug codeBrian Paul2009-04-031-50/+84
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* i965: added brw_same_reg()Brian Paul2009-04-031-0/+7
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