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* i965: remove _NEW_ACCUMBrian Paul2011-01-231-1/+0
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* r300/compiler: remove any code related to relative addressing of temporariesMarek Olšák2011-01-239-120/+13
| | | | | The hw can't do it and the code was useless anyway (it's lowered in the GLSL compiler).
* glsl, i965: Remove unnecessary talloc includes.Kenneth Graunke2011-01-213-3/+0
| | | | These are already picked up by ir.h or glsl_types.h.
* r600c: get OQ results only for 4 DBs on r600 classAndre Maasikas2011-01-211-2/+6
| | | | | - since evergreen addition which increased this to 8 depth backends other bytes may contain garbage values
* intel: Fix typeos from 3d028024 and 790ff232Ian Romanick2011-01-202-15/+15
| | | | ...and remove egg from face.
* i915: Set correct values for range/precision of fragment shader typesIan Romanick2011-01-201-0/+14
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* i965: Set correct values for range/precision of fragment shader typesIan Romanick2011-01-201-0/+9
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* r600c: bump sq gpr resources if a shader needs more than defaultAndre Maasikas2011-01-202-0/+21
| | | | | | | | | | | | | ideally this should be set once in the beginning of CS but there's no way to change values there while in the middle of rendering. For now reemitting SQ setup seems to work probably due to r700WaitForIdleClean after each render currently does not to try to decrease values once increased fixes hangs in glsl-vs-vec4-indexing-temp-src-in-nested-loop-combined glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined for my rv740 maybe more for other chips
* r200: fix up some problems with TFP on r200Dave Airlie2011-01-201-5/+15
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* i965/fs: Take the shared mathbox into account in instruction scheduling.Eric Anholt2011-01-191-0/+15
| | | | | | I don't have evidence for this amounting to any improvement, but it does codify a bit more what we understand so far about the pipeline.
* i965/fs: Add a helper function for detecting math opcodes.Eric Anholt2011-01-192-8/+13
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* i965/fs: Assign URB/CURB register numbers after instruction scheduling.Eric Anholt2011-01-191-2/+3
| | | | | | | | | | | | This fixes a bunch of unnecessary barriers due to the scheduler not knowing what that arbitrary register description refers to when trying to reason about its dependencies. The result is rescheduling in the convolution kernel shader in Lightsmark, which results in avoiding register spilling and increasing the performance of the first scene from 6-7 fps midway through the panning to 11fps. The register spilling was a regression from Mesa 7.9 to Mesa 7.10.
* i965/fs: Add an instruction scheduler.Eric Anholt2011-01-194-0/+479
| | | | | | | Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also reschedules the giant multiply tree at the end of glsl-fs-convolution-1 so that we end up not spilling registers, producing the expected level of performance.
* i965/fs: Add a helper for detecting texturing opcodes.Eric Anholt2011-01-192-8/+12
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* radeon: avoid segfault on 3D textures.Dave Airlie2011-01-191-0/+3
| | | | This is a candidate for 7.9 and 7.10
* radeon: oops didn't need this logbase2 fnDave Airlie2011-01-191-15/+0
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* radeon: calculate complete texture state inside TFP functionDave Airlie2011-01-191-3/+25
| | | | | | (really not sure why I'm doing this). This is a candidate for 7.9 and 7.10 branches.
* dri/nouveau: allow multiple maps of surface buffersBen Skeggs2011-01-191-2/+4
| | | | | | | | | Can happen during swrast fallbacks if a buffer is somehow bound as a render target and a texture. Fixes gnome-shell on nv20, and gets it mostly working on nv10. Signed-off-by: Ben Skeggs <[email protected]>
* radeon/r200: fix fbo-clearmipmap + gen-teximageDave Airlie2011-01-193-6/+6
| | | | | | | | | | | sw clears were being used and not getting the correct offsets in the span code. also not emitting correct offsets for CB draws to texture levels. (I've no idea why I'm playing with r100). This is a candidate for 7.9 and 7.10
* i965: Fix a comment typo.Eric Anholt2011-01-181-1/+1
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* i965: Fix a bug in i965 compute-to-MRF.Eric Anholt2011-01-181-0/+1
| | | | | | Fixes piglit glsl-fs-texture2d-branching. I couldn't come up with a testcase that didn't involve dead code, but it's still worthwhile to fix I think.
* r600c: preserve correct buffer when using fboAndre Maasikas2011-01-181-1/+1
| | | | Hopefully better than previous - this passes more mipgen tests
* r600: set border color as RGBAAndre Maasikas2011-01-181-2/+2
| | | | border color is RGBA for samples - this passes texenv tests
* r600c: use STATE_FB_WPOS_Y_TRANSFORM variable to do wpos transformAndre Maasikas2011-01-181-7/+9
| | | | | use introduced STATE_FB_WPOS_Y_TRANSFORM variable (thanks Marek) this gets coords also right when using fbo
* i965: Fix dead pointers to fp->Parameters->ParameterValues[] after realloc.Eric Anholt2011-01-172-10/+36
| | | | | | | Fixes texrect-many regression with ff_fragment_shader -- as we added refs to the subsequent texcoord scaling paramters, the array got realloced to a new address while our params[] still pointed at the old location.
* i965: add support for EXT_texture_sRGB_decodeDave Airlie2011-01-162-3/+12
| | | | | | | We just choose the texture format depending on the srgb decode bit for the sRGB formats. Signed-off-by: Dave Airlie <[email protected]>
* mesa: begin implementation of GL_ARB_draw_buffers_blendBrian Paul2011-01-1519-111/+111
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* intel: Expose GL_ARB_ES2_compatibility.Eric Anholt2011-01-141-0/+2
| | | | | | | | We don't have all of the features of this extension hooked up yet, but the consensus yesterday was that since those features are things that we should also be supporting in our ES2 implementation, claiming ES2 here too doesn't make anything worse and will make incremental improvement through piglit easier.
* i965: Replace broken handling of dead code with an assert.Eric Anholt2011-01-141-10/+12
| | | | | | This code should never have been triggered, but I often did anyway when I disabled optimization passes during debugging, then spent my time debugging that this code doesn't work.
* i965: Add an invalidation of live intervals after register splitting.Eric Anholt2011-01-141-0/+1
| | | | No effect, since it was called before live intervals were calculated.
* i915: Fix compiler warning from sw fallback removal change.Eric Anholt2011-01-141-1/+1
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* i965: fix fbo-srgb on i965.Dave Airlie2011-01-141-0/+5
| | | | | | | Until we get the EXT_framebuffer_sRGB extension we should bind the sRGB formats for FBO as linear. Signed-off-by: Dave Airlie <[email protected]>
* i915: Disable extension OES_standard_derivativesChad Versace2011-01-131-0/+13
| | | | | OES_standard_derivatives must be manually disabled for i915 because Mesa enables it by default.
* i965: Remove unnecessary headers.Vinson Lee2011-01-131-2/+0
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* dri_util: fail driCreateNewScreen if InitScreen is NULLPaulo Zanoni2011-01-131-0/+3
| | | | | | | | | Without this, X doesn't start with UMS on r300g. NOTE: This is a candidate for the 7.9 and 7.10 branches. Signed-off-by: Paulo Zanoni <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* i965/fs: Do flat shading when appropriate.Eric Anholt2011-01-122-20/+42
| | | | | We were trying to interpolate, which would end up doing unnecessary math, and doing so on undefined values. Fixes glsl-fs-flat-color.
* i965: Clarify when we need to (re-)calculate live intervals.Eric Anholt2011-01-123-5/+27
| | | | | | The ad-hoc placement of recalculation somewhere between when they got invalidated and when they were next needed was confusing. This should clarify what's going on here.
* i965/vs: When MOVing to produce ABS, strip negate of the operand.Eric Anholt2011-01-121-0/+1
| | | | | We were returning the negative absolute value, instead of the absolute value. Fixes glsl-vs-abs-neg.
* i965/fs: When producing ir_unop_abs of an operand, strip negate.Eric Anholt2011-01-121-0/+1
| | | | | We were returning the negative absolute value, instead of the absolute value. Fixes glsl-fs-abs-neg.
* i965: Tighten up the check for flow control interfering with coalescing.Eric Anholt2011-01-111-12/+26
| | | | | | This greatly improves codegen for programs with flow control by allowing coalescing for all instructions at the top level, not just ones that follow the last flow control in the program.
* i965: Remove dead fallback for stencil _Enabled but no stencil buffer.Eric Anholt2011-01-111-8/+0
| | | | | The _Enabled field is the thing that takes into account whether there's a stencil buffer. Tested with piglit glx-visuals-stencil.
* r600c: add evergreen ARL support.Alberto Milone2011-01-111-14/+69
| | | | Signed-off-by: Alberto Milone <[email protected]>
* i965: Use a new miptree to avoid software fallbacks due to drawing offset.Eric Anholt2011-01-102-40/+67
| | | | | | | | | When attaching a small mipmap level to an FBO, the original gen4 didn't have the bits to support rendering to it. Instead of falling back, just blit it to a new little miptree just for it, and let it get revalidated into the stack later just like any other new teximage. Bug #30365.
* intel: Drop the speculatively-use-firstImage-mt in validation.Eric Anholt2011-01-101-17/+0
| | | | | It's been replaced by just setting texObj->mt to image->mt at TexImage time.
* intel: Don't relayout the texture on maxlevel change.Eric Anholt2011-01-101-7/+6
| | | | | | | This avoids relayouts in the common case of glGenerateMipmap() or people doing similar things. Bug #30366.
* intel: When making a new teximage miptree, make a full one.Eric Anholt2011-01-101-79/+68
| | | | | | | | If we hit this path, we're level 1+ and the base level got allocated as a single level instead of a full tree (so we don't match intelObj->mt). This tries to recover from that so that we end up with 2 allocations and 1 validation blit (old -> new) instead of allocations equal to number of levels and levels - 1 blits.
* Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."Eric Anholt2011-01-1010-82/+152
| | | | | | | | | | | This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663. This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa. I was wrong about which generations supported baselevel adjustment -- it's just gen4, nothing earlier. This meant that i915 would have never used the mag filter when baselevel != 0. Not a severe bug, but not an intentional regression. I think we can fix the performance issue another way.
* i965: Add #defines for HiZ and separate stencil buffer commands.Kenneth Graunke2011-01-101-0/+3
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* i965: Add new HiZ related bits to WM_STATE.Kenneth Graunke2011-01-101-1/+8
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* i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.Kenneth Graunke2011-01-103-22/+22
| | | | Again, this makes it match the documentation.
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