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* i965: Force X-tiling for 128 bpp formats on Sandybridge.Kenneth Graunke2013-08-151-0/+9
* i915,i965: Fix memory leak in try_pbo_upload (v2)Vinson Lee2013-08-152-0/+2
* i965: allow 8 user clip planes on CTG+Chris Forbes2013-08-165-6/+21
* i965: get rid of clip plane compactionChris Forbes2013-08-164-55/+11
* i965/clip: Support clip distances for line clippingChris Forbes2013-08-161-19/+47
* i965/clip: remove spurious clipvertex paramChris Forbes2013-08-161-11/+4
* i965/clip: Use clip distances for all user clippingChris Forbes2013-08-161-5/+6
* i956/clip: push dp4 into load_clip_distanceChris Forbes2013-08-161-17/+22
* i965/clip: Track offset into the vertex for clipdistanceChris Forbes2013-08-162-0/+12
* i965/Gen4-5: Set clip flags from clip distancesChris Forbes2013-08-161-11/+11
* i965: add new VS_OPCODE_UNPACK_FLAGS_SIMD4X2Chris Forbes2013-08-164-1/+29
* i965/vs: add vec4_instruction::depends_on_flagsChris Forbes2013-08-162-2/+7
* i965/clip: Enable interpolation of clip distancesChris Forbes2013-08-161-7/+3
* i965/vs: Do legacy clip lowering earlierChris Forbes2013-08-162-20/+15
* i965/Gen4-5: ensure VUE slots for clipdistance are valid if user clipping is ...Chris Forbes2013-08-161-0/+5
* i965/gen7+: Fix build error introduced by renaming upload_3dstate_so_decl_list.Paul Berry2013-08-131-1/+1
* i965: Move arrays brw_multisample_positions* to new headerChad Versace2013-08-132-46/+73
* i965: Refactor names of sample_positions_8/4x arraysChad Versace2013-08-131-7/+7
* i965/gen7+: Mark upload_3dstate_so_decl_list as non-static (v2)Kenneth Graunke2013-08-132-3/+7
* i965: Mark a few brw_draw_upload.c functions as non-staticKenneth Graunke2013-08-132-7/+14
* i965/fs: Add dump_instruction() support for ARF destinations.Kenneth Graunke2013-08-121-0/+6
* i965/fs: Remove extraneous newline in dump_instruction() for CMP.Kenneth Graunke2013-08-121-1/+1
* i965/fs: Optimize IF/MOV/ELSE/MOV/ENDIF to SEL when possible.Kenneth Graunke2013-08-122-0/+79
* i965/fs: Consider predicated SEL instructions as whole variable writes.Kenneth Graunke2013-08-121-1/+1
* i965/fs: Explicitly disallow CSE on predicated instructions.Kenneth Graunke2013-08-121-1/+3
* i965/fs: Log a performance warning if skipping 16-wide due to pulls.Kenneth Graunke2013-08-121-7/+11
* i965: add missing BRW_NEW_INTERPOLATION_MAP to state dumpChris Forbes2013-08-101-0/+1
* i965: Add a new debug mode for the VUE mapChris Forbes2013-08-103-0/+29
* i965: Remember to call intel_prepare_render() before blitting.Kenneth Graunke2013-08-081-0/+5
* i965: Add #defines for the MI_LOAD_REGISTER_MEM command.Kenneth Graunke2013-08-061-0/+4
* i965: Initialize the intel_context::bufmgr pointer earlier.Kenneth Graunke2013-08-061-2/+1
* i965: Tidy preprocessor macros for SO_PRIM_STORAGE_NEEDED registers.Kenneth Graunke2013-08-061-5/+2
* i965: Tidy preprocessor macros for SO_NUM_PRIMS_WRITTEN registers.Kenneth Graunke2013-08-062-7/+4
* i965: Don't allocate curbe buffers on Gen6+.Kenneth Graunke2013-08-061-2/+4
* intel_fbo: remove unused intel_renderbuffer hiz functionsJordan Justen2013-08-042-26/+0
* i965 clear/draw: set renderbuffer attachment as needing depth resolveJordan Justen2013-08-042-2/+4
* i965: add intel_renderbuffer_att_set_needs_depth_resolveJordan Justen2013-08-042-0/+18
* i965: add intel_miptree_set_all_slices_need_depth_resolveJordan Justen2013-08-042-0/+16
* i965 gen7: don't set FORCE_ZERO_RTAINDEX for layered renderingJordan Justen2013-08-041-1/+1
* hsw hiz: Remove x/y offset restriction for hizJordan Justen2013-08-041-24/+0
* gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2013-08-044-66/+45
* gen7 fbo: make unmatched depth/stencil configs return unsupportedJordan Justen2013-08-041-0/+16
* hsw hiz: Add new size restrictions for miplevels > 0Jordan Justen2013-08-041-3/+13
* gen7 blorp depth: calculate base surface width/heightJordan Justen2013-08-041-0/+13
* gen7 depth surface: calculate minimum array element being renderedJordan Justen2013-08-042-0/+17
* gen7 depth surface: calculate LOD being rendered toJordan Justen2013-08-042-0/+6
* gen7 depth surface: calculate depth (array size) for depth surfaceJordan Justen2013-08-042-0/+5
* gen7 depth surface: calculate more specific surface typeJordan Justen2013-08-042-0/+47
* i965: init global state first in brw_workaround_depthstencil_alignmentJordan Justen2013-08-041-5/+14
* i965: Initialize the maximum number of GS threads on Haswell.Kenneth Graunke2013-08-021-0/+3
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