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path: root/src/mesa/drivers/dri
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* python: Better iterate over dictionariesMathieu Bridon2018-07-241-2/+2
* intel/compiler: Account for built-in uniforms in analyze_ubo_rangesJason Ekstrand2018-07-235-5/+5
* i965/misc: Use depth/stencil surf's tiling on gen4-5Nanley Chery2018-07-191-1/+3
* intel/blorp: Take an explicit filter parameter in blorp_blitJason Ekstrand2018-07-181-2/+61
* i965: Sweep NIR after linking phase to free held memoryDanylo Piliaiev2018-07-181-0/+2
* intel/blorp: fix uninitialized variable warningCaio Marcelo de Oliveira Filho2018-07-181-3/+3
* i965/miptree: avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho2018-07-181-1/+2
* i965: batchbuffer: write correct canonical offset with softpinLionel Landwerlin2018-07-181-1/+2
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-6/+6
* i965/miptree: Allocate MS texture BOs as BUSYNanley Chery2018-07-131-2/+2
* i965/miptree: Inline make_separate_stencilNanley Chery2018-07-131-23/+6
* i965/miptree: Init r8stencil_needs_update to falseNanley Chery2018-07-131-3/+4
* i965/miptree: Refactor miptree_createNanley Chery2018-07-131-36/+12
* i965/miptree: Add and use mt_surf_usageNanley Chery2018-07-131-13/+25
* i965/miptree: Share alloc_flags in miptree_createNanley Chery2018-07-131-7/+4
* i965/miptree: Share the miptree format in miptree_createNanley Chery2018-07-131-15/+15
* i965/miptree: Share tiling_flags in miptree_createNanley Chery2018-07-131-8/+7
* i965/miptree: Delete MIPTREE_CREATE_LINEARNanley Chery2018-07-132-13/+3
* i965/miptree: Use make_surface in map_blitNanley Chery2018-07-131-6/+6
* i965/draw: Fix adding the stencil bo to the depth cacheNanley Chery2018-07-131-1/+1
* i965/draw: Set the r8stencil flag after drawingNanley Chery2018-07-131-1/+11
* i965/miptree: Set the r8stencil flag in map_depthstencilNanley Chery2018-07-131-1/+3
* i965: Set the r8stencil flag in miptree_finish_writeNanley Chery2018-07-134-17/+4
* i965/miptree: Use the correct BLT pitchNanley Chery2018-07-121-6/+6
* i965/miptree: Drop an if case from retile_as_linearNanley Chery2018-07-121-4/+0
* i965: Make blt_pitch publicNanley Chery2018-07-122-10/+12
* i965: fix typo (wrong gen number) in commentCaio Marcelo de Oliveira Filho2018-07-121-1/+1
* i965: Support saving the gen program with glGetProgramBinaryJordan Justen2018-07-091-6/+66
* i965: Add flag_state param to brw_search_cacheJordan Justen2018-07-0912-45/+35
* mesa: Add gl_shader_program param to ProgramBinarySerializeDriverBlobJordan Justen2018-07-093-1/+12
* i965: Add brw_populate_default_keyJordan Justen2018-07-0912-73/+195
* i965: Replace brw_setup_tex_for_precompile brw with devinfoJordan Justen2018-07-098-9/+8
* i965: Regenerate blob without gen program for shader cacheJordan Justen2018-07-091-1/+63
* i965: Add support for driver cache blob containing the gen programJordan Justen2018-07-091-0/+41
* i965: Use brw_prog_key_set_id in disk cache load/store codeJordan Justen2018-07-091-16/+8
* i965: Add brw_prog_key_set_id helper to set the program id on any stageJordan Justen2018-07-092-0/+19
* i965: Add brw_stage_cache_id to map gl stages to brw cache_idsJordan Justen2018-07-092-0/+17
* i965: Add brw_(read|write)_blob_program_data functionsJordan Justen2018-07-093-41/+61
* i965: Add brw_program_deserialize_driver_blobJordan Justen2018-07-093-21/+48
* i965: Move brw_program_*serialize_nir to brw_program_binary.cJordan Justen2018-07-092-37/+37
* i965: Use ShaderCacheSerializeDriverBlob driver functionJordan Justen2018-07-093-11/+7
* i965/icl: Don't set float blend optimization bit in CACHE_MODE_SSAnuj Phogat2018-07-091-4/+0
* swrast: Fix eglMakeCurrent(dpy, NULL, NULL, ctx) (v2)Adam Jackson2018-07-091-21/+20
* i965: fix clear color bo address relocationLionel Landwerlin2018-07-071-1/+1
* i965: Use the new nir atomic counter linker for SPIR-V shadersNeil Roberts2018-07-031-0/+2
* i965: enable AtomicStorage capability for gen7+Alejandro Piñeiro2018-07-031-0/+1
* i965: Fix BRW_NEW_NUM_SAMPLES to be in .brw, not .mesaKenneth Graunke2018-07-021-2/+2
* st/mesa/i965: Allow decompressing ETC2 to GL_RGBATomeu Vizoso2018-07-021-1/+1
* intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaroundJason Ekstrand2018-06-281-0/+17
* intel/fs: Add fields to wm_prog_data for SIMD32 dispatchJason Ekstrand2018-06-282-0/+3
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