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* i965: Add tr_mode and mip tail information in surface state dumpAnuj Phogat2015-12-231-2/+5
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen8/cs: Gen8 requires 64 byte alignment for push constant dataJordan Justen2015-12-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BDW PRM Vol2a: Command Reference: Instructions, section MEDIA_CURBE_LOAD, says that 'CURBE Total Data Length' and 'CURBE Data Start Address' are 64-byte aligned. This is different from previous gens, that were 32-byte aligned. v2 (Jordan): - CURBE Data Start Address is also 64-byte aligned. - The call to brw_state_batch should also use 64-byte alignment. - Improve PRM reference. v3: * New patch from Jordan. Always align base and size to 64 bytes. Fixes the following SSBO CTS tests on BDW: ES31-CTS.shader_storage_buffer_object.basic-atomic-case1-cs ES31-CTS.shader_storage_buffer_object.basic-operations-case1-cs ES31-CTS.shader_storage_buffer_object.basic-operations-case2-cs ES31-CTS.shader_storage_buffer_object.basic-stdLayout_UBO_SSBO-case2-cs ES31-CTS.shader_storage_buffer_object.advanced-write-fragment-cs ES31-CTS.shader_storage_buffer_object.advanced-indirectAddressing-case2-cs ES31-CTS.shader_storage_buffer_object.advanced-matrix-cs And many other CS CTS tests as reported by Marta Lofstedt. (Commit message is from Iago, but in v3, code is from Jordan.) Signed-off-by: Jordan Justen <[email protected]> Tested-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable ARB_tessellation_shader on Gen8+.Kenneth Graunke2015-12-221-0/+1
| | | | | | | | | | | | | | | | | | Everything is in place and I'm not aware of any further issues. Tested with: - Piglit - Tessmark - Unigine Heaven - Shadow of Mordor - GRID Autosport I have patches to backport this to Haswell, Ivybridge, and Baytrail as well (the first Intel hardware to support tessellation), but there are still a lot of GPU hangs left to debug. So that will come later. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Handle mix-and-match TCS/TES with separate shader objects.Kenneth Graunke2015-12-228-24/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GL_ARB_separate_shader_objects allows the application to mix-and-match TCS and TES programs separately. This means that the interface between the two stages isn't known until the final SSO pipeline is in place. This isn't a great match for our hardware: the TCS and TES have to agree on the Patch URB entry layout. Since we store data as per-patch slots followed by per-vertex slots, changing the number of per-patch slots can significantly alter the layout. This can easily happen with SSO. To handle this, we store the [Patch]OutputsWritten and [Patch]InputsRead bitfields in the TCS/TES program keys, introducing program recompiles. brw_upload_programs() decides the layout for both TCS and TES, and passes it to brw_upload_tcs/tes(), which store it in the key. When creating the NIR for a shader specialization, we override nir->info.inputs_read (and friends) to the program key's values. Since everything uses those, no further compiler changes are needed. This also replaces the hack in brw_create_nir(). To avoid recompiles, brw_precompile_tes() looks to see if there's a TCS in the linked shader. If so, it accounts for the TCS outputs, just as brw_upload_programs() would. This eliminates all recompiles in the non-SSO case. In the SSO case, there should only be recompiles when using a TCS and TES that have different input/output interfaces. Fixes Piglit's mix-and-match-tcs-tes test. v2: Pull the brw_upload_programs code into a brw_upload_tess_programs() helper function (requested by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Defer input lowering for tessellation stages until specialization.Kenneth Graunke2015-12-224-27/+22
| | | | | | | | | | | | | | | | | | | | With tessellation shaders and SSO, we won't be able to always decide on VUE map layouts at LinkProgram time. Unfortunately, we have to delay it until shader specialization time. However, uniform lowering cannot be deferred - brw_codegen_*_prog() reads nir->num_uniforms. Fortunately, we don't need to defer it - uniform, system value, atomic, and sampler lowering can safely stay where it is. This patch moves those to brw_lower_nir()'s only caller, renames brw_lower_nir() to brw_nir_lower_io(), and introduces calls to that. For non-tessellation stages, I chose to call brw_nir_lower_io() from brw_create_nir(), so it's still done at the same time. There's no need to defer it, and doing it at LinkProgram time is nice. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Automatically create a passthrough TCS when needed.Kenneth Graunke2015-12-223-12/+113
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Start program_string_id from 1, not 0.Kenneth Graunke2015-12-221-0/+1
| | | | | | | | | This way, I can safely use brw_tcs_prog_key::program_string_id == 0 to mean "not filled out because no program exists", which avoids the need for adding an extra boolean to that struct. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Create and set a new brw_tcs_prog_data::outputs_written field.Kenneth Graunke2015-12-222-6/+14
| | | | | | | | | | | When the application hasn't supplied a TCS, and we have to create one, we need to know what VS outputs to copy to TES inputs. To do this, we create a new program key field, and set it to the TES InputsRead bitfield. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Upload HS push constants whenever default tess. levels change.Kenneth Graunke2015-12-223-0/+5
| | | | | | | | | | | | | When using tessellation on OpenGL without a TCS, default values for gl_TessLevelOuter/gl_TessLevelInner are provided via the API. Core Mesa will flag ctx->DriverFlags.NewDefaultTessLevels whenever those values change. We add a corresponding BRW_NEW_DEFAULT_TESS_LEVELS flag and hook it up to HS push constants (which will be used to upload these default values to the autogenerated TCS). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Only call _mesa_load_state_parameters if prog exists.Kenneth Graunke2015-12-221-1/+2
| | | | | | | | With the automatic-TCS creation, we won't have a prog, but still need to upload push constants. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Switch TCS gl_program/gl_shader_program checks over to TES.Kenneth Graunke2015-12-223-4/+5
| | | | | | | | | | | | | | | Tessellation control shaders are optional, but evaluation shaders will always be present when using tessellation. However, we'll always enable the TCS (HS) hardware stage when using tessellation - we'll just create a program on the fly. That program, however, won't have a gl_program or gl_shader_program. So we shouldn't check brw->tess_ctrl_program or shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] - if we want to know whether tessellation is enabled, we should look for a TES. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Remove unnecessary brw->tess_ctrl_program assertions.Kenneth Graunke2015-12-225-6/+1
| | | | | | | | | | | | | This is trying to enforce the fact that the hardware requires HS, TE, and DS to be enabled or disabled together. But it's kind of an ad-hoc attempt, and not too useful. More importantly, we aren't going to have a gl_shader_program for the TCS which is automatically generated when none is present. (We'll just handle it in the driver backend.) So, these will trip for no reason. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Consolidate BRW_NEW_TESS_{CTRL,EVAL}_PROGRAM flags.Kenneth Graunke2015-12-2214-47/+37
| | | | | | | | | | | | | | | | | | | | | | | | For several reasons, I don't think it's particularly useful to have separate flags: 1. Most of the time, tessellation shaders are paired, so both will be replaced at the same time. 2. The data layout is tightly coupled. Both need to agree on the number of per-patch slots in the VUE map. Even adding extra TCS outputs that aren't read by the TES will trigger the need for recompiles. 3. The TCS is optional from an API perspective, but required by the hardware whenever tessellation is enabled. So, atoms that deal with the TCS must check brw->tess_eval_program (BRW_NEW_TESS_EVAL_PROGRAM?) rather than brw->tess_ctrl_program to tell whether tessellation is enabled. So, not only is it unlikely to be useful, it's a bit confusing to get right. Simply using one flag for both simplifies this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Only call brw_upload_tcs/tes_prog when using tessellation.Kenneth Graunke2015-12-223-24/+13
| | | | | | | | | | | If there's no evaluation shader, tessellation is disabled. The upload functions would just bail. Instead, don't bother calling them. This will simplify the optional-TCS case a bit, as brw_upload_tcs can assume that we're doing tessellation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Ensure FS execution in presence of atomic buffersIago Toral Quiroga2015-12-222-5/+6
| | | | | | | | | | | | | | | | | | | | | | On Haswell we need to set the UAV_ONLY WM state bit when there are no colour or depth buffer writes and on all hardware we should set the early depth/stencil control field to PSEXEC unless early fragment tests are enabled to make sure that the fragment shader is executed regardless of whether per-fragment tests pass or not as the spec requires. So far we have been doing this for images only, but we should apply the same treatment to all side effectful scenarios. Suggested by Curro. This is not strictly required for compliance with the original ARB_shader_atomic_counters extension, it's only necessary to get the execution semantics specified in GL4.2+ right. v2: - Mark active_fs_has_side_effects as constant. (Curro) - Mention that this is only only necessary to get the execution semantics specified in GL4.2+ right. (Curro) Reviewed-by: Francisco Jerez <[email protected]>
* mesa: Add a _mesa_active_fragment_shader_has_side_effects helperIago Toral Quiroga2015-12-222-7/+2
| | | | | | | | | | | | | | | Some drivers can disable the FS unit if there is nothing in the shader code that writes to an output (i.e. color, depth, etc). Right now, mesa has a function to check for atomic buffers and the i965 driver also checks for images. Refactor this logic into a generic function that we can use for any source of side effects in a fragment shader. Suggested by Jason. v2: - Use '_Shader', as suggested by Tapani, to fix the following CTS test: ES31-CTS.shader_atomic_counters.advanced-usage-many-draw-calls2 Reviewed-by: Francisco Jerez <[email protected]>
* i965: Implement gl_PatchVerticesIn by baking it into brw_tcs_prog_key.Kenneth Graunke2015-12-223-1/+12
| | | | | | | | | | | | | | | | | | The hardware provides us no decent way of getting at the number of input vertices in the patch topology from the tessellation control shader. It's actually very surprising - normally this sort of information would be available in the thread payload. For the precompile, we guess that the number of vertices will be the same for both the input and output patches. This usually seems to be the case. On Gen8+, we could pass in an extra push constant containing this value. We may be able to do that on Haswell too. It's quite a bit trickier on Ivybridge, however. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation control shaders.Kenneth Graunke2015-12-2219-2/+1195
| | | | | | | | | | | | | | | | | | | | | | | | | The TCS is the first tessellation shader stage, and the most complicated. It has access to each of the control points in the input patch, and computes a new output patch. There is one logical invocation per output control point; all invocations run in parallel, and can communicate by reading and writing output variables. One of the main responsibilities of the TCS is to write the special gl_TessLevelOuter[] and gl_TessLevelInner[] output variables which control how much new geometry the hardware tessellation engine will produce. Otherwise, it simply writes outputs that are passed along to the TES. We run in SIMD4x2 mode, handling two logical invocations per EU thread. The hardware doesn't properly manage the dispatch mask for us; it always initializes it to 0xFF. We wrap the whole program in an IF..ENDIF block to handle an odd number of invocations, essentially falling back to SIMD4x1 on the last thread. v2: Update comments (requested by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation evaluation shadersKenneth Graunke2015-12-2213-3/+627
| | | | | | | | | | | | | | | | | | | The TES is essentially a post-tessellator VS, which has access to the entire TCS output patch, and a special gl_TessCoord input. Otherwise, they're very straightforward. This patch implements SIMD8 tessellation evaluation shaders for Gen8+. The tessellator can generate a lot of geometry, so operating in SIMD8 mode (8 vertices per thread) is more efficient than SIMD4x2 mode (only 2 vertices per thread). I have another patch which implements SIMD4x2 mode for older hardware (or via an environment variable override). We currently handle all inputs via the pull model. v2: Improve comments (suggested by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nouveau: enable use of new kernel interfacesBen Skeggs2015-12-221-2/+0
| | | | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Samuel Pitoiset <[email protected]>
* nouveau: remove use of deprecated nouveau_device_wrap()Ben Skeggs2015-12-222-1/+18
| | | | | | | | | | | | | | Switching to the newer libdrm entry-points tells libdrm that it's OK to make use of newer kernel interfaces. We want to be able to isolate any bugs to either the interfaces changes, or the use of NVIF itself. As such, this commit has a slight hack which forces libdrm to continue using the older kernel interfaces. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Samuel Pitoiset <[email protected]>
* i965: Only apply CS stall workaround pre-SKLBen Widawsky2015-12-211-2/+4
| | | | | | | As per the docs. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Optimize predicate handling for any/all.Matt Turner2015-12-182-18/+77
| | | | | | | | | | | | | | | | | | For a select whose condition is any(v), instead of emitting cmp.nz.f0(8) null<1>D g1<0,4,1>D 0D mov(8) g7<1>.xUD 0x00000000UD (+f0.any4h) mov(8) g7<1>.xUD 0xffffffffUD cmp.nz.f0(8) null<1>D g7<4,4,1>.xD 0D (+f0) sel(8) g8<1>UD g4<4,4,1>UD g3<4,4,1>UD we now emit cmp.nz.f0(8) null<1>D g1<0,4,1>D 0D (+f0.any4h) sel(8) g9<1>UD g4<4,4,1>UD g3<4,4,1>UD Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Delete bany, ball, fany, fall.Matt Turner2015-12-183-23/+0
| | | | | | | | | | | As in the previous patches, these can be implemented as any(v) -> any_nequal(v, false) all(v) -> all_equal(v, true) and their removal simplifies the code in the next patch. Reviewed-by: Ian Romanick <[email protected]>
* glsl: Remove ir_unop_any.Matt Turner2015-12-181-17/+0
| | | | | | | The GLSL IR to TGSI/Mesa IR paths for any_nequal have the same optimizations the ir_unop_any paths had. Reviewed-by: Ian Romanick <[email protected]>
* i965/screen: Allow OpenGLES 3.1 for gen8+Jordan Justen2015-12-161-0/+5
| | | | | | | | OpenGLES 3.1 cannot be enabled for gen 7 (Ivy Bridge, Haswell) since they are still missing ARB_stencil_texturing. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* i965: Enable compute shaders in more cases for OpenGLES 3.1Jordan Justen2015-12-161-1/+4
| | | | | | | | Previously we were checking the desktop OpenGL ARB_compute_shader requirements, but for OpenGLES 3.1, the requirements are lower. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* Revert "i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals"Neil Roberts2015-12-161-6/+7
| | | | | | | | | | | | | | | | | | | | This reverts commit 839793680f99b8387bee9489733d5071c10f3ace. The patch was breaking DRI3 because driGLFormatToImageFormat does not handle MESA_FORMAT_B8G8R8X8_SRGB which ended up making it fail to create the renderbuffer and it would later crash. It's not trivial to add this format because there is no __DRI_IMAGE_FORMAT nor __DRI_IMAGE_FOURCC define for the format either. I'm not sure how difficult adding this would be and whether adding a new format would require some sort of new version for DRI. Seeing as this might take a while to fix I think it makes sense to just revert the patch in the meantime in order to avoid regressing master. It is also not handled in intel_gles3_srgb_workaround and there may be other cases where it breaks. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93388 Acked-by: Jason Ekstrand <[email protected]>
* i965: Fix crash when calling glViewport with no surface boundNeil Roberts2015-12-161-2/+4
| | | | | | | | | | | | | If EGL_KHR_surfaceless_context is used then glViewport can be called with NULL for the draw and read surfaces. This was previously causing a crash because the i965 driver tries to use this point to invalidate the surfaces and it was derferencing the NULL pointer. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93257 Cc: Nanley Chery <[email protected]> Cc: "11.1" <[email protected]> Tested-by: Nanley Chery <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965: Allocate URB space for HS and DS stages when required.Chris Forbes2015-12-153-36/+170
| | | | | | | | | | | | | | | | | | | | v2: (by Ken, incorporating feedback from Matt Turner): - Rewrite the push constant allocation code to be clearer. - Only apply the minimum VS entries workaround on Gen 8. v3: (by Ken) - Fix a bug in v2 where we failed to allocate the full push constant space when the number of enabled stages didn't divide the available push constant space evenly. (Any left over space is now allocated to the PS, as it was in v1.) - Fix an off-by-one error in v2's number of enabled stages calculation. - Use DIV_ROUND_UP for nicer formatting. - Line wrapping fixes. Signed-off-by: Chris Forbes <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Use DIV_ROUND_UP() in gen7_urb.c code.Kenneth Graunke2015-12-141-9/+8
| | | | | | | This is a newer convention, which we prefer over ALIGN(x, n) / n. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Make TES inputs match TCS outputs.Kenneth Graunke2015-12-141-0/+11
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Force VS -> TCS varyings to use the SSO VUE map layout.Kenneth Graunke2015-12-142-2/+5
| | | | | | | | | | | | The compact VUE map only works when varying packing is in use. Unfortunately, varying packing is disabled for TCS inputs. This is needed to fix Piglit's tcs-input-read-array-interface test. v2: Make lines fit in 80 columns (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Handle TCS outputs and TES inputs.Kenneth Graunke2015-12-141-2/+112
| | | | | | | | | | | | | | | | | | TCS outputs and TES inputs both refer to a common "patch URB entry" shared across all invocations. First, there are some number of per-patch entries. Then, there are per-vertex entries accessed via an offset for the variable and a stride times the vertex index. Because these calculations need to be done in both the vec4 and scalar backends, it's simpler to just compute the offset calculations in NIR. It doesn't necessarily make much sense to use per-vertex intrinsics afterwards, but that at least means we don't lose the per-patch vs. per-vertex information. v2: Use is_input/is_output helpers (suggested by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Handle TCS inputs and TES outputs.Kenneth Graunke2015-12-141-1/+3
| | | | | | | | | | | | TES outputs work exactly like VS outputs, so we can simply add a case statement for those. TCS inputs are very similar to geometry shaders - they're arrays of per-vertex data. We use the same method I used for the scalar GS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader VUE map code.Kenneth Graunke2015-12-142-7/+107
| | | | | | | Based on a patch by Chris Forbes, but largely rewritten by Ken. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix partial variable access for geometry shaders in SSO mode.Kenneth Graunke2015-12-141-4/+34
| | | | | | | | | | | | | Without varying packing, if a VS writes a compound variable, and the GS only reads part of it, the base location of the variable may not actually be in the VUE map. To cope with this, we do lowering in terms of varying slots, add any constant offsets to the base, and then do the VUE map remapping. This ensures we only look up VUE map entries for slots which actually exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Separate base offset/constant offset combining from remapping.Kenneth Graunke2015-12-141-25/+70
| | | | | | | | | | My tessellation branch has two additional remap functions. I don't want to replicate this logic there. v2: Handle inputs/outputs separately (suggested by Jason Ekstrand). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visualsNeil Roberts2015-12-131-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Previously if the visual didn't have an alpha channel then it would pick a format that is not sRGB-capable. I don't think there's any reason not to always have an sRGB-capable visual. Since 28090b30 there are now visuals advertised without an alpha channel which means that games that don't request alpha bits in the config would end up without an sRGB-capable visual. This was breaking supertuxkart which assumes the winsys buffer is always sRGB-capable. The previous code always used an RGBA format if the visual config itself was marked as sRGB-capable regardless of whether the visual has alpha bits. I think we don't actually advertise any sRGB-capable visuals (but we just use sRGB formats anyway) so it shouldn't make any difference. However this patch also changes it to use RGBX if an sRGB-capable visual is requested without alpha bits for consistency. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92759 Cc: "11.0 11.1" <[email protected]> Cc: Ilia Mirkin <[email protected]> Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add B8G8R8X8_SRGB to the alpha format overrideNeil Roberts2015-12-131-0/+4
| | | | | | | | | | | brw_init_surface_formats overrides the render format for RGBX formats which aren't supported for rendering so that they internally use RGBA instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a renderable format. This patch just adds it. Cc: "11.0 11.1" <[email protected]> Cc: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_formatNeil Roberts2015-12-131-0/+1
| | | | | | | | | This will be used in a subsequent patch as the format for RGB visuals. Cc: "11.0 11.1" <[email protected]> Cc: Ilia Mirkin <[email protected]> Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use the correct source for local memory load offsetsJason Ekstrand2015-12-111-1/+1
| | | | | | | | | | The offset for loads is in src[0]. This was a copy+paste error in the nir_intrinsic_load/store refactoring. This commit fixes a segfault in ES31-CTS.compute_shader.work-group-size. I have no idea how piglit failed to catch this... Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93348 Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add Gen8+ tessellation control shader state (3DSTATE_HS).Kenneth Graunke2015-12-111-13/+51
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add Gen7+ tessellation engine state (3DSTATE_TE).Kenneth Graunke2015-12-111-8/+28
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add Gen8+ tessellation evaluation shader state (3DSTATE_DS).Kenneth Graunke2015-12-111-7/+59
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader push constant support.Kenneth Graunke2015-12-117-29/+63
| | | | | | | Based on a patch by Chris Forbes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader sampler support.Kenneth Graunke2015-12-114-1/+51
| | | | | | | Based on code by Chris Forbes and Fabian Bieler. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader surface support.Kenneth Graunke2015-12-1110-11/+389
| | | | | | | | | | | | This is brw_gs_surface_state.c copy and pasted twice with search and replace. brw_binding_table.c code is similarly copy and pasted. v2: Drop dword_pitch related fields. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Make fs_visitor::emit_urb_writes set EOT for TES as well.Kenneth Graunke2015-12-111-1/+1
| | | | | | | | | | | | | Tessellation evaluation shaders work almost identically to vertex shaders - we have a set of URB writes at the end of the program, and the last one should terminate it. Geometry shaders really are the special case, where multiple EmitVertex() calls trigger URB writes in the middle of the program. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Don't hardcode g1 for URB handles in fs_visitor::emit_urb_writes().Kenneth Graunke2015-12-111-4/+5
| | | | | | | | | Tessellation evaluation shaders will use g4 instead. For now, make an fs_reg called urb_handle and use that in place of hardcoding g1. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
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