| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel: Add missing header. | Vinson Lee | 2010-07-29 | 1 | -0/+1 |
| | | | | | Add context.h for NEED_SECONDARY_COLOR symbol. | ||||
| * | dri: Add missing header to dri_metaops.c. | Vinson Lee | 2010-07-29 | 1 | -0/+1 |
| | | | | | Add context.h for FLUSH_VERTICES symbol. | ||||
| * | intel: Declare the various tracked state variables using "extern" | Kristian Høgsberg | 2010-07-29 | 1 | -62/+62 |
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| * | intel: Don't depend on context config values when picking texture formats | Kristian Høgsberg | 2010-07-29 | 1 | -24/+12 |
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| * | r600: since 8744c36e added asserts - use another random register for shader ↵ | Andre Maasikas | 2010-07-29 | 1 | -1/+1 |
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| * | intel: Implement EGL_KHR_surfaceless extension | Kristian Høgsberg | 2010-07-28 | 1 | -7/+20 |
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| * | intel: Remove unused intel/server files | Kristian Høgsberg | 2010-07-27 | 5 | -397/+2 |
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| * | i965: Fix reversed naming of the operations in compute-to-mrf optimization. | Eric Anholt | 2010-07-26 | 3 | -6/+11 |
| | | | | | | Also fix up comments, so that the difference between the two passes is clarified. | ||||
| * | i965: Clean up a few magic numbers to use brw_defines.h defs. | Eric Anholt | 2010-07-26 | 3 | -18/+20 |
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| * | i965: Use MIN2, MAX2 instead of rolling our own. | Eric Anholt | 2010-07-26 | 1 | -15/+12 |
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| * | i965: Fold the "is arithmetic" bit of 965 opcodes into the opcode list. | Eric Anholt | 2010-07-26 | 1 | -50/+26 |
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| * | i965: Remove some duped register size/count definitions | Eric Anholt | 2010-07-26 | 2 | -34/+26 |
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| * | i965: Move the GRF-to-MRF optimizations to brw_optimize.c. | Eric Anholt | 2010-07-26 | 3 | -619/+618 |
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| * | i965: Improve (i.e. remove) some grf-to-mrf unnecessary moves | Benjamin Segovia | 2010-07-26 | 1 | -2/+626 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | Several routines directly analyze the grf-to-mrf moves from the Gen binary code. When it is possible, the mov is removed and the message register is directly written in the arithmetic instruction Also redundant mrf-to-grf moves are removed (frequently for example, when sampling many textures with the same uv) Code was tested with piglit, warsow and nexuiz on an Ironlake machine. No regression was found there Note that the optimizations are *deactivated* on Gen4 and Gen6 since I did test them properly yet. No reason there are bugs but who knows The optimizations are currently done in branch free programs *only*. Considering branches is more complicated and there are actually two paths: one for branch free programs and one for programs with branches Also some other optimizations should be done during the emission itself but considering that some code is shader between vertex shaders (AOS) and pixel shaders (SOA) and that we may have branches or not, it is pretty hard to both factorize the code and have one good set of strategies | ||||
| * | i965: Allow VS MOVs to use immediate constants. | Eric Anholt | 2010-07-26 | 1 | -0/+1 |
| | | | | | | Clarifies program assembly, and with a little tweak to always use constant_map, we could cut down on constant buffer payload. | ||||
| * | i965: Cleanly fail programs with unsupported array access. | Eric Anholt | 2010-07-23 | 1 | -1/+28 |
| | | | | | | This should be more useful for developers and for bug triaging than just generating wrong code. | ||||
| * | i965: Add support for VS relative addressing of temporary arrays. | Eric Anholt | 2010-07-23 | 1 | -2/+49 |
| | | | | | Fixes glsl-vs-arrays. Bug #27388. | ||||
| * | i965: Respect VS/VP point size result when enabled. | Eric Anholt | 2010-07-22 | 1 | -3/+4 |
| | | | | | Fixes glsl-vs-point-size. | ||||
| * | i965: Fix the disasm output for da16 src widths. | Eric Anholt | 2010-07-22 | 1 | -1/+1 |
| | | | | | | | This has confused me twice now. It's a fixed width of 4 (usually a region description of <4,4,1>), not 1. If it was 1, we'd have been skipping all over register space. | ||||
| * | i965: Avoid extra MOV in VS indirect register reads. | Eric Anholt | 2010-07-22 | 1 | -15/+16 |
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| * | i965: Fix up VS temporary array access for fixed index offset != 0. | Eric Anholt | 2010-07-22 | 1 | -1/+1 |
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| * | r600: Flip point sprite coordinates when rendering to an FBO. | Henri Verbeet | 2010-07-22 | 1 | -1/+3 |
| | | | | | This supersedes http://lists.freedesktop.org/archives/mesa-dev/2010-July/001442.html. | ||||
| * | i965: In the VS, multiply the address reg by the appropriate register size. | Eric Anholt | 2010-07-21 | 1 | -27/+14 |
| | | | | | | | | | | | | | The ARL value is increments of vec4 in the register file. But PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved between the two verts being executed (thus a vec8 each), compared to PROGRAM_STATE_VAR being packed vec4s. Fixes: glsl-vs-arrays-2 glsl-vs-mov-after-deref (without regressing glsl-vs-arrays-3) | ||||
| * | i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support. | Eric Anholt | 2010-07-21 | 3 | -52/+31 |
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| * | i965: Support relative addressed VS constant reads using the appropriate msg. | Eric Anholt | 2010-07-21 | 3 | -31/+66 |
| | | | | | | The previous support was overly complicated by trying to use the same 1-OWORD message for both offsets. | ||||
| * | i965: Fix the DP read msg_control definitions other than plain OWORD. | Eric Anholt | 2010-07-21 | 1 | -6/+16 |
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| * | i965: Clean up dead code from the VS get_constant/get_reladdr_constant split. | Eric Anholt | 2010-07-21 | 1 | -3/+1 |
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| * | i956: Set the execution size correctly for scratch space writes. | Eric Anholt | 2010-07-21 | 1 | -2/+2 |
| | | | | | | | | | Otherwise, the second half isn't written, and we end up reading back black. Fixes the remaining junk drawn in glsl-max-varyings, and will likely help with a number of large real-world shaders. | ||||
| * | i965: Set the GEM domain flags for the scratch space. | Eric Anholt | 2010-07-21 | 1 | -1/+1 |
| | | | | | | | They go into the render cache, so while we don't care about their contents after execution, failing to note them could cause the writes to be flushed over important buffer contents later. | ||||
| * | i965: Use the pretty define for 4-oword DP reads. | Eric Anholt | 2010-07-21 | 1 | -1/+1 |
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| * | i965: Set the send commit bit on register spills as required pre-gen6. | Eric Anholt | 2010-07-21 | 1 | -9/+32 |
| | | | | | Otherwise, the subsequent read may not get the written value. | ||||
| * | i965: Add disasm for dataport reads (register unspilling). | Eric Anholt | 2010-07-21 | 1 | -1/+22 |
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| * | i965: Remove an unused variable. | Carl Worth | 2010-07-21 | 1 | -1/+0 |
| | | | | | To quiet a compiler warning. | ||||
| * | radeon: Remove unnecessary header. | Vinson Lee | 2010-07-20 | 1 | -1/+0 |
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| * | glx: Remove support for MESA_swap_frame_usage | Kristian Høgsberg | 2010-07-19 | 7 | -42/+0 |
| | | | | | | The extension never worked, the implementation returns GLX_BAD_CONTEXT when enabling the frame tracking. | ||||
| * | glx: Drop support for GLX_MESA_allocate_memory | Kristian Høgsberg | 2010-07-19 | 3 | -124/+0 |
| | | | | | Only r200 implemented it. | ||||
| * | i965: Mostly fix glsl-max-varyings. | Eric Anholt | 2010-07-19 | 1 | -10/+20 |
| | | | | | | | | | There was confusion on both the size of message we can send, and on what the URB destination offset means. The remaining problems appear to be due to spilling of regs in the fragment shader being broken. | ||||
| * | i965: Clean up message register setup in emit_vertex_write(). | Eric Anholt | 2010-07-19 | 1 | -7/+7 |
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| * | i965: Reduce repeated calculation of the attribute-offset-in-VUE. | Eric Anholt | 2010-07-19 | 4 | -24/+19 |
| | | | | | | | This cleans up some chipset dependency sprinkled around, and fixes a potential overflow of the attribute offset array for many vertex results. | ||||
| * | i965: Clarify the nr_regs calculation in brw_clip.c | Eric Anholt | 2010-07-19 | 1 | -3/+8 |
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| * | i965: Don't set up VUE space for the disabled user clip distances on gen6. | Eric Anholt | 2010-07-19 | 2 | -8/+14 |
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| * | r600: fix typo in r700 assembler | Alex Deucher | 2010-07-15 | 1 | -1/+1 |
| | | | | | | | Noticed by Henri Verbeet on IRC. NOTE: This is a candidate for the 7.8 branch. | ||||
| * | radeon: Also flush if it's not the current context that's being destroyed. | Henri Verbeet | 2010-07-15 | 1 | -1/+1 |
| | | | | | | | | This avoids calling radeonFlush() during context destruction, when ctx->DrawBuffer would be NULL. NOTE: This is a candidate for the 7.8 branch. | ||||
| * | radeon: allow driconf vblank settings with dri2 | Alex Deucher | 2010-07-15 | 1 | -0/+1 |
| | | | | | | | | fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28771 NOTE: This is a candidate for the 7.8 branch. | ||||
| * | r300/compiler: fix swizzling in the transformation of Abs modifiers | Marek Olšák | 2010-07-14 | 1 | -2/+2 |
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| * | r300/compiler: implement the Abs source operand modifier for vertex shaders | Marek Olšák | 2010-07-13 | 1 | -4/+55 |
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| * | r300/compiler: emulate SIN/COS/SCS in r3xx-r4xx vertex shaders | Marek Olšák | 2010-07-13 | 1 | -1/+7 |
| | | | | | Despite the docs, the corresponding hardware instructions are r5xx-only. | ||||
| * | Merge branch 'master' of git://anongit.freedesktop.org/mesa/mesa | Maciej Cencora | 2010-07-12 | 1 | -1/+1 |
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| | * | r600: Fix include recursion. | Vinson Lee | 2010-07-12 | 1 | -1/+1 |
| | | | | | | | | | | | Fix r600_context.h -> r700_oglprog.h -> r600_context.h include recursion. | ||||
| * | | radeon: fix some wine d3d9 tests | Maciej Cencora | 2010-07-12 | 1 | -0/+9 |
| |/ | | | | | | | | | Need to flush command stream before mapping texture image that is referenced by current cs. Candidate for 7.8 branch. Signed-off-by: Maciej Cencora <[email protected]> | ||||
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