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path: root/src/mesa/drivers/dri
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* Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"Emil Velikov2015-12-193-31/+10
* Revert "i965/fs: Use a stride of 1 and byte offsets for UBOs"Emil Velikov2015-12-193-13/+16
* Revert "i965/vec4: Use a stride of 1 and byte offsets for UBOs"Emil Velikov2015-12-193-7/+27
* Revert "i965/state: Get rid of dword_pitch arguments to buffer functions"Emil Velikov2015-12-195-14/+30
* Revert "i965/nir: Remove unused indirect handling"Emil Velikov2015-12-191-11/+33
* i965: Add B8G8R8X8_SRGB to the alpha format overrideNeil Roberts2015-12-181-0/+4
* i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_formatNeil Roberts2015-12-181-0/+1
* i965: Resolve color and flush for all active shader images in intel_update_st...Francisco Jerez2015-12-181-0/+18
* i965/nir: Remove unused indirect handlingJason Ekstrand2015-12-181-33/+11
* i965/state: Get rid of dword_pitch arguments to buffer functionsJason Ekstrand2015-12-185-30/+14
* i965/vec4: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-183-27/+7
* i965/fs: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-183-16/+13
* i965/vec4: Use byte offsets for UBO pulls on Sandy BridgeJason Ekstrand2015-12-183-10/+31
* i965: use _Shader to get fragment program when updating surface stateTapani Pälli2015-12-181-2/+2
* i965: Fix scalar vertex shader struct outputs.Kenneth Graunke2015-12-182-6/+32
* i965: Fix fragment shader struct inputs.Kenneth Graunke2015-12-183-82/+84
* xmlconfig: Add support for DragonFlyFrançois Tigeot2015-12-031-0/+3
* meta: Track VBO using gl_buffer_object instead of GL API object handleIan Romanick2015-11-241-4/+5
* meta: Don't leave the VBO bound after _mesa_meta_setup_vertex_objectsIan Romanick2015-11-241-1/+1
* i965: Use _mesa_NamedBufferSubData for users of _mesa_meta_setup_vertex_objectsIan Romanick2015-11-241-3/+3
* i965: Don't pollute the buffer object namespace in brw_meta_fast_clearIan Romanick2015-11-241-5/+5
* i965: Use internal functions for buffer object accessIan Romanick2015-11-241-6/+18
* i965: Use DSA functions for VBOs in brw_meta_fast_clearIan Romanick2015-11-241-6/+7
* i965: Pass brw_context instead of gl_context to brw_draw_rectlistIan Romanick2015-11-241-4/+5
* r200: fix bgrx8/xrgb8 blitsRoland Scheidegger2015-11-181-0/+4
* radeon: fix bgrx8/xrgb8 blitsRoland Scheidegger2015-11-181-0/+2
* i965/skl/gt4: Fix URB programming restriction.Ben Widawsky2015-11-181-0/+9
* i965/skl: Add GT4 PCI IDsBen Widawsky2015-11-071-1/+5
* nouveau: set MaxDrawBuffers to the same value as MaxColorAttachmentsIlia Mirkin2015-11-071-1/+1
* i965: Fix missing BRW_NEW_*_PROG_DATA flagging caused by cache reuse.Kenneth Graunke2015-11-052-4/+5
* i965: Fix is-renderable check in intel_image_target_renderbuffer_storageIan Romanick2015-11-051-5/+1
* i965: Remove early release of DRI2 miptreeChris Wilson2015-10-211-1/+0
* i965/vec4: fill src_reg type using the constructor type parameterAlejandro Piñeiro2015-10-211-0/+2
* i965/vec4: check writemask when bailing out at register coalesceAlejandro Piñeiro2015-10-211-4/+6
* i965: Use _mesa_is_image_unit_valid() instead of gl_image_unit::_Valid.Francisco Jerez2015-10-213-6/+10
* i965: Don't tell the hardware about our UAV access.Francisco Jerez2015-10-216-19/+41
* i915: Remember to call intel_prepare_render() before blittingVille Syrjälä2015-10-071-0/+5
* i915: Fix texcoord vs. varying collision in fragment programsVille Syrjälä2015-10-072-26/+71
* i830: Fix collision between I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0)Ville Syrjälä2015-10-071-4/+4
* i965/fs: Fix hang on IVB and VLV with image format mismatch.Francisco Jerez2015-10-071-4/+38
* i965: Respect stride and subreg_offset for ATTR registersKristian Høgsberg Kristensen2015-09-281-1/+4
* t_dd_dmatmp: Make "count" actually be the countIan Romanick2015-09-232-2/+2
* i965: fix textureGrad for cubemapsTapani Pälli2015-09-231-19/+182
* i965/vec4_nir: Load constants as integersAntia Puentes2015-09-231-2/+2
* i965/vec4: Fix saturation errors when coalescing registersAntia Puentes2015-09-231-0/+21
* i965/vec4: Don't reswizzle hardware registersJason Ekstrand2015-09-231-0/+8
* i965: Use hash tables for brw_fs_vector_splitting().Kenneth Graunke2015-09-111-22/+22
* i965: Advertise 65536 for GL_MAX_UNIFORM_BLOCK_SIZE.Kenneth Graunke2015-09-111-0/+9
* xmlpool: 'promote' LOCALEDIR variableEmil Velikov2015-09-111-1/+1
* i965: Disallow fast blit paths for CopyTexImage with PixelTransfer opsChris Wilson2015-09-112-0/+8
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