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path: root/src/mesa/drivers/dri
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* i965: Support decoding INTERFACE_DESCRIPTOR_DATA with INTEL_DEBUG=batJordan Justen2017-11-211-0/+24
* i965: Optimize bucket index calculationAravindan Muthukumar2017-11-201-8/+39
* i965: Mark BOs as external when we export their handleJason Ekstrand2017-11-173-1/+11
* i965/bufmgr: Add a helper to mark a BO as externalJason Ekstrand2017-11-171-6/+11
* i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.Kenneth Graunke2017-11-171-1/+5
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-171-1/+1
* i965: Remove DWord length from MI_FLUSH_DW definitionAnuj Phogat2017-11-171-1/+1
* i965: Upload invariant state once at the start of the batch on Gen4-5.Kenneth Graunke2017-11-164-13/+3
* meson: Add dridriverdir variable to dri.pc.Rafael Antognolli2017-11-161-0/+1
* i915: add missing extensions.h includeEmil Velikov2017-11-162-0/+2
* mesa: split extensions overrides and glGetString(GL_EXTENSIONS)Emil Velikov2017-11-166-0/+6
* i965: remove ARB_compute_shader extension overrideEmil Velikov2017-11-161-2/+1
* i965: use _mesa_is_desktop_gl helperEmil Velikov2017-11-161-1/+1
* i965: Implement another VF cache invalidate workaround on Gen8+.Kenneth Graunke2017-11-161-8/+33
* i965: Drop some reserved space remnants.Kenneth Graunke2017-11-152-4/+1
* i965: Fold ABO state upload code into the SSBO/UBO state upload code.Kenneth Graunke2017-11-1510-189/+16
* i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.Kenneth Graunke2017-11-153-11/+8
* i965: Make a better helper function for UBO/SSBO/ABO surface handling.Kenneth Graunke2017-11-153-94/+37
* i965: Make use of brw_load_register_imm32() helper functionAnuj Phogat2017-11-145-40/+19
* i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DWAnuj Phogat2017-11-142-5/+19
* i965: Program DWord Length in MI_FLUSH_DWAnuj Phogat2017-11-142-2/+2
* i965: implement (un)mapImageJulien Isorce2017-11-141-2/+63
* i965: Track the depth and render caches separatelyJason Ekstrand2017-11-135-22/+26
* i965/blorp: Add more destination flushingJason Ekstrand2017-11-131-1/+6
* i965: Add more precise cache tracking helpersJason Ekstrand2017-11-136-13/+49
* i965: Add stencil buffers to cache set regardless of stencil texturingJason Ekstrand2017-11-131-3/+1
* i965: Switch over to fully external-or-not MOCS schemeJason Ekstrand2017-11-133-29/+11
* i965: Use PTE MOCS for all external buffersJason Ekstrand2017-11-132-10/+18
* intel/blorp: Make the MOCS setting part of blorp_addressJason Ekstrand2017-11-132-15/+26
* i965/gen10: Use the correct form of | for the RCPFE workaroundJason Ekstrand2017-11-101-2/+2
* i965: Make L3 configuration atom listen for TCS/TES program updates.Kenneth Graunke2017-11-101-0/+2
* mesa: enable ARB_texture_buffer_* extensions in the Compatibility profileMarek Olšák2017-11-091-3/+5
* i965: Pretend there are 4 subslices for compute shader threads on Gen9+.Kenneth Graunke2017-11-091-1/+13
* i965: expose SRGB visuals and turn on EGL_KHR_gl_colorspaceTapani Pälli2017-11-093-7/+26
* i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTEKenneth Graunke2017-11-081-0/+1
* intel/nir: Break the linking code into a helper in brw_nir.cJason Ekstrand2017-11-081-34/+4
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-071-3/+3
* i965: disable NIR linking on HSW and belowTimothy Arceri2017-11-071-1/+4
* i965: Enable flush controlNeil Roberts2017-11-062-1/+21
* dri: Add a flush control extensionNeil Roberts2017-11-062-2/+21
* dri: Change __DriverApiRec::CreateContext to take a struct for attribsNeil Roberts2017-11-0612-103/+128
* intel: Don't flush the old context in intelMakeCurrentNeil Roberts2017-11-062-18/+0
* i965/gen10: Implement Wa3DStateModeAnuj Phogat2017-11-032-0/+16
* i965/gen10: Enable float blend optimizationAnuj Phogat2017-11-032-0/+9
* i965/gen10: Implement WaForceRCPFEHangWorkaroundAnuj Phogat2017-11-031-0/+23
* i965/gen10: Implement WaSampleOffsetIZ workaroundAnuj Phogat2017-11-032-0/+50
* i965/gen10: Don't set Antialiasing Enable in 3DSTATE_RASTER if num_samples > 1Anuj Phogat2017-11-031-0/+10
* i965/gen10: Don't set Smooth Point Enable in 3DSTATE_SF if num_samples > 1Anuj Phogat2017-11-031-1/+12
* i965: perf: list registers to program for queriesLionel Landwerlin2017-11-032-0/+66
* i965: perf: factorize code for availabilityLionel Landwerlin2017-11-031-12/+16
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