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* i965/gen8: Use HALIGN_16 for single sample mcs buffersBen Widawsky2015-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code meant to do this, but was only checking num_samples == 1 to figure out if a surface was fast clear capable. However, we can allocate single sample miptrees with num_samples == 0 (when it's an internally created buffer). This fixes a bunch of the piglit tests on gen8. Other gens should have been fine. Here is the order of events that allowed this to slip through: t0: I wrote halign patches and tested them. These alignment assertions are for gen8 fast clear surfaces, basically. t1: I pushed bogus perf patch which made fast clears never happen t2: Reworked halign patches based on Chad's feedback and introduced the bug this patch fixes. t2.5: I tested reworked patches, but assertion wasn't hit because of t1. t3. Matt fixed issue in t1 which made fast clears happen here: commit 22af95af8316f2888a3935cdf774ff0997b3dd42 Author: Matt Turner <[email protected]> Date: Thu Jun 18 16:14:50 2015 -0700 i965: Add missing braces around if-statement. This logic should match that of the v1 of my halign patch series. Cc: Kenneth Graunke <[email protected]> Cc: Matt Turner <[email protected]> Reported-by: Kenneth Graunke <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Tested-by: Mark Janes <[email protected]>
* i965: Add missing braces around if-statement.Matt Turner2015-06-181-1/+2
| | | | | | | | | | Fixes a performance problem caused by commit b639ed2f. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90895
* i965/compute: Fix undefined code with right_mask for SIMD32Jordan Justen2015-06-181-1/+1
| | | | | | | | | Although we don't support SIMD32, krh pointed out that the left shift by 32 is undefined by C/C++ for 32-bit integers. Suggested-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix textureGrad with cube samplersIago Toral Quiroga2015-06-181-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't use sampler messages with gradient information (like sample_g or sample_d) to deal with this scenario because according to the PRM: "The r coordinate and its gradients are required only for surface types that use the third coordinate. Usage of this message type on cube surfaces assumes that the u, v, and gradients have already been transformed onto the appropriate face, but still in [-1,+1] range. The r coordinate contains the faceid, and the r gradients are ignored by hardware." Instead, we should lower this to compute the LOD manually based on the gradients and use a different sample message that takes the computed LOD instead of the gradients. This is already being done in brw_lower_texture_gradients.cpp, but it is restricted to shadow samplers only, although there is a comment stating that we should probably do this also for samplerCube and samplerCubeArray. Because of this, both dEQP and Piglit test cases for textureGrad with cube maps currently fail. This patch does two things: 1) Activates the texturegrad lowering pass for all cube samplers. 2) Corrects the computation of the LOD value for cube samplers. I had to do 2) because for cube maps the calculations implemented in the lowering pass always compute a value of rho that is twice the value we want (so we get a LOD value one unit larger than we want). This only happens for cube map samplers (all kinds). I am not sure about why we need to do this, but I suspect that it is related to the fact that cube map coordinates, when transported to a specific face in the cube, are in the range [-1, 1] instead of [0, 1] so we probably need to divide the derivatives by 2 when we compute the LOD. Doing that would produce the same result as dividing the final rho computation by 2 (or removing a unit from the computed LOD, which is what we are doing here). Fixes the following piglit tests: bin/tex-miplevel-selection textureGrad Cube -auto -fbo bin/tex-miplevel-selection textureGrad CubeArray -auto -fbo bin/tex-miplevel-selection textureGrad CubeShadow -auto -fbo Fixes 10 dEQP tests in the following category: dEQP-GLES3.functional.shaders.texture_functions.texturegrad.*cube* Reviewed-by: Ben Widawsky <[email protected]>
* i965: enable ARB_framebuffer_no_attachments for Gen7+Kevin Rogovin2015-06-172-0/+7
| | | | | | | Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* i965: execution of frag-shader when it has atomic bufferKevin Rogovin2015-06-172-0/+7
| | | | | | | | Ensure that the GPU spawns the fragment shader thread for those fragment shaders with atomic buffer access. Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* i965: Use _mesa_geometric_ functions appropriatelyKevin Rogovin2015-06-1716-34/+70
| | | | | | | | | | | | | | Change references to gl_framebuffer::Width, Height, MaxNumLayers and Visual::samples to use the _mesa_geometry_ convenience functions for those places where the geometry of the gl_framebuffer is needed (in contrast to the geometry of the intersection of the attachments of the gl_framebuffer). This patch is to pave the way to enable GL_ARB_framebuffer_no_attachments on Gen7 and higher in i965. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* i965/gen9: Disable Mip Tail for YF/YS tiled surfacesAnuj Phogat2015-06-162-2/+11
| | | | | | | | | | | | | | | Disabling miptails fixed the buffer corruption happening in FBO which use YF/YS tiled renderbuffer or texture as color attachment. Spec recommends disabling mip tails only for non-mip-mapped surfaces. But, without disabling miptails I couldn't get correct data out of mipmapped YF/YS tiled surface. We need better understanding of miptails before start using them. For now this patch helps move things forward. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Set vertical and horizontal surface alignmentsAnuj Phogat2015-06-161-6/+26
| | | | | | | | | | Patch sets the alignments for texture and renderbuffer surfaces. V3: Make changes inside horizontal_alignment() and vertical_alignment() (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*Anuj Phogat2015-06-161-3/+3
| | | | | | | | Makes no functional changes in the code. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Rename use_linear_1d_layout() and make it globalAnuj Phogat2015-06-162-5/+9
| | | | | | | | | This function will be utilised in later patches. V2: Make both pointers constants (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Set tiled resource mode in surface stateAnuj Phogat2015-06-162-0/+27
| | | | | | | | This patch sets the tiled resource mode for texture and renderbuffer surfaces. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Fix the source register for indexed samplersNeil Roberts2015-06-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously when setting up the sample instruction for an indirect sampler the vec4 backend was directly passing the pseudo opcode's src0. However vec4_visitor::visit(ir_texture *) doesn't set the texture operation's src0 -- it's left as BAD_FILE, which when translated into a brw_reg gives the null register. In brw_SAMPLE, gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and sets the src0 appropriately. The indirect sampler case did not have a call to gen6_resolve_implied_move(). The fs backend avoids this because the platforms that support dynamic indexing of samplers (IVB+) have been converted to not use the fake-MRF hack, and instead send from proper GRFs. This patch makes it call gen6_resolve_implied_move before setting up the indirect message. This is similar to what is done for constant sampler numbers in brw_SAMPLE. The Piglit tests for sampler array indexing didn't pick this up because they were using a texture with a solid colour so it didn't matter what texture coordinates were actually used. The tests have now been changed to be more thorough in this commit: http://cgit.freedesktop.org/piglit/commit/?id=4f9caf084eda7 With that patch the tests for gs and vs are currently failing on Ivybridge, but this patch fixes them. There are no other changes to a Piglit run on Ivybridge. On Skylake the gs tests were failing even without the Piglit patch because Skylake needs the source registers to work correctly in order to send a message header to select SIMD4x2 mode. (The explanation in the commit message is partially written by Matt Turner) Tested-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix aligning to the block size in intel_miptree_copy_sliceNeil Roberts2015-06-161-2/+4
| | | | | | | | | | | | | | | | | | This function was trying to align the width and height to a multiple of the block size for compressed textures. It was using align_w/h as a shortcut to get the block size as up until Gen9 this always happens to match. However in Gen9+ the alignment values are expressed as multiples of the block size so in effect the alignment values are always 4 for compressed textures as that is the minimum value we can pick. This happened to work for most compressed formats because the block size is also 4, but for FXT1 this was breaking because it has a block width of 8. This fixes some Piglit tests testing FXT1 such as spec@3dfx_texture_compression_fxt1@fbo-generatemipmap-formats Reviewed-by: Nanley Chery <[email protected]>
* i965: Check for miptree pitch alignment before using ↵Anuj Phogat2015-06-151-1/+3
| | | | | | | | | | intel_miptree_map_movntdqa() We have an assert() in intel_miptree_map_movntdqa() which expects the pitch to be 16 byte aligned. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Remove break after returnAnuj Phogat2015-06-151-3/+0
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965/gen8+: Add aux buffer alignment assertionsBen Widawsky2015-06-121-0/+22
| | | | | | | | | | | | | | This helped find the incorrect HALIGN values from the previous patches. v2: Add PRM references for assertions (Chad) v3: Remove duplicated part of commit message, assert num_samples > 1, instead of num_samples > 0. (Chad) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen9: Set HALIGN_16 for all aux buffersBen Widawsky2015-06-121-3/+19
| | | | | | | | | | | | | | | | | | | Just like the previous patch, but for the GEN9 constraints. v2: bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address this, move the check to where the gen8 check is, and do the appropriate conditional there. v3: Remove stray whitespace introduced in v2 (Chad) Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part about gen7 (Chad). Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> (v1) Reviewed-by: Jordan Justen <[email protected]> (v1) Reviewed-by: Chad Versace <[email protected]>
* i965/gen8: Correct HALIGN for AUX surfacesBen Widawsky2015-06-123-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This restriction was attempted in this commit: commit 47053464630888f819ef8cc44278f1a1220159b9 Author: Anuj Phogat <[email protected]> Date: Fri Feb 13 11:21:21 2015 -0800 i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT However, the commit itself doesn't achieve the desired goal as determined by the asserts which the next patch adds. mcs_mt is NULL (never set) we're in the process of allocating the mcs_mt miptree when we get to this function. I didn't check, but perhaps this would work with blorp, however, meta clears allocate the miptree structure (which AFAICT needs the alignment also) way before it allocates using meta clears where the renderbuffer is allocated way before the aux buffer. The restriction is referenced in a few places, but the most concise one [IMO] from the spec is for Gen9. Gen8 loosens the restriction in that it only requires this for non-msrt surface. When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must be used. With the code before the miptree layout flag rework (patches preceding this), accomplishing this workaround is very difficult. v2: bugfix: Don't set HALIGN16 for gens before 8 (Chad) v3: non-trivial rebase Signed-off-by: Ben Widawsky <[email protected]> Cc: Neil Roberts <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Extract tiling from fast clear decisionBen Widawsky2015-06-122-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several constraints when determining if one can fast clear a surface. Some of these are alignment, pixel density, tiling formats, and others that vary by generation. The helper function which exists today does a suitable job, however it conflates "BO properties" with "Miptree properties" when using tiling. I consider the former to be attributes of the physical surface, things which are determined through BO allocation, and the latter being attributes which are derived from the API, and having nothing to do with the underlying surface. Determining tiling properties and creating miptrees are related operations (when we allocate a BO for a miptree) with some disjoint constraints. By extracting the decisions into two distinct choices (tiling vs. miptree properties), we gain flexibility throughout the code to make determinations about when we can or cannot fast clear strictly on the miptree. To signify this change, I've also renamed the function to indicate it is a distinction made on the miptree. I am torn as to whether or not it was a good idea to remove "non_msrt" since it's a really nice thing for grep. v2: Reword some comments (Chad) intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad) Make full if ladder for gens in above function (Chad) Signed-off-by: Ben Widawsky <[email protected]> Cc: Topi Pohjolainen <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen9: Only allow Y-Tiled MCS buffersBen Widawsky2015-06-121-0/+2
| | | | | | | | | | | | | | | | | | | For GEN9, much of the logic to use X-Tiled buffers has been stripped out. It is still supported in some places, but it's never desirable. Unfortunately we don't yet have the ability to have Y-Tiled scanout (see: http://patchwork.freedesktop.org/patch/46984/), NOTE: This patch shouldn't actually do anything since SKL doesn't yet use fast clears (they are disabled because they are causing regressions). THerefore, the only case we can get to this function on SKL is by way of intel_update_winsys_renderbuffer_miptree. v2: Update commit message to be more clear that the NOTE is for SKL only. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-129-75/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I think pretty much everyone agrees that having more than a single bool as a function argument is bordering on a bad idea. What sucks about the current code is in several instances it's necessary to propagate these boolean selections down to lower layers of the code. This requires plumbing (mechanical, but still churn) pretty much all of the miptree functions each time. By introducing the flags paramater, it is possible to add miptree constraints very easily. The use of this, as is already the case, is sometimes we have some information at the time we create the miptree that needs to be known all the way at the lowest levels of the create/allocation, disable_aux_buffers is currently one such example. There will be another example coming up in a few patches. v2: Tab fix. (Ben) Long line fixes (Topi) Use anonymous enum instead of #define for layout flags (Chad) Use 'X != 0' instead of !!X (everyone except Chad) v3: Some non-trivial conflict resolution on top of Anuj's patches. Signed-off-by: Ben Widawsky <[email protected]> Cc: "Pohjolainen, Topi" <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/nir: Support barrier intrinsic functionJordan Justen2015-06-121-0/+4
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Implement support for ir_barrierJordan Justen2015-06-125-0/+45
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add brw_barrier to emit a Gateway Barrier SENDJordan Justen2015-06-122-0/+32
| | | | | | | | | | | | This will be used to implement the Gateway Barrier SEND needed to implement the barrier function. v2: * notify => gateway_notify (Ken) * combine short lines of brw_barrier proto/decl (mattst88) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add brw_WAIT to emit wait instructionJordan Justen2015-06-122-0/+23
| | | | | | | | | | | This will be used to implement the barrier function. v2: * Rename to brw_WAIT (mattst88) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add notification registerJordan Justen2015-06-121-0/+16
| | | | | | | | | | | | This will be used by the wait instruction when implementing the barrier() function. v2: * Changes suggested by mattst88 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Disassemble Gateway SEND messagesJordan Justen2015-06-121-0/+16
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/inst: Add gateway_notify and gateway_subfuncid fieldsJordan Justen2015-06-121-3/+11
| | | | | | | | | | | | | | | These fields will be used when emitting a send for the barrier function. Reference: IVB PRM Volume 4, Part 2, Section 1.1.1 Message Descriptor v2: * notify => gateway_notify (Ken) * define bits for gen4-gen6 (bwidawsk, Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add GATEWAY_SFID definitionsJordan Justen2015-06-121-0/+8
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* glsl: Add ir node for barrierChris Forbes2015-06-122-0/+7
| | | | | | | | | v2: * Changes suggested by mattst88 [[email protected]: Add nir support] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/cs: Use exec all for CS terminateJordan Justen2015-06-121-1/+2
| | | | | | | | | This prevents an assertion from being hit with SIMD16: Assertion `inst->exec_size == dispatch_width() || force_writemask_all' failed. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Fix unused variable warningChad Versace2015-06-121-1/+2
| | | | | | Annotate offset_components with attribute 'unused'. Reviewed-by: Matt Turner <[email protected]>
* mesa: build xmlconfig to a separate static libraryErik Faye-Lund2015-06-126-4/+14
| | | | | | | | | | | | | | | | | | | | As we use the file from both the dri modules and loader, we end up with multiple definition of the symbols provided in our gallium dri modules. Additionally we compile the file twice. Resolve both issues, effectively enabling the build on toolchains which don't support -Wl,--allow-multiple-definition. v2: [Emil Velikov] - Fix the Scons/Android build. - Resolve libgbm build issues (bring back the missing -lm) Cc: Julien Isorce <[email protected]> Cc: "10.5 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90310 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90905 Acked-by: Matt Turner <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965/fs: Remove one more fixed brw_null_reg() from the visitor.Francisco Jerez2015-06-121-1/+1
| | | | | | | | | | Instead use fs_builder::null_reg_f() which has the correct register width. Avoids the assertion failure in fs_builder::emit() hit by the "ES3-CTS.shaders.loops.for_dynamic_iterations.unconditional_break_fragment" GLES3 conformance test introduced by 4af4cfba9ee1014baa4a777660fc9d53d57e4c82. Reported-and-reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."Kenneth Graunke2015-06-111-5/+1
| | | | | | | | | | | | | This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043. The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4. interpolation.lines_wide" test appears to be broken on Cherryview when we expose line widths greater than 12.0. I'm not sure why. For now, just go back to the limits we used on older platforms. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902 Acked-by: Matt Turner <[email protected]>
* i965: Re-index SSA definitions before printing NIR code.Kenneth Graunke2015-06-111-0/+6
| | | | | | | | | | This makes the SSA definitions use sequential numbers (0, 1, 2, ...) instead of seemingly random ones. There's not much point normally, but it makes debug output much easier to read. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965/gen8: Fix antialiased line rendering with width < 1.5Iago Toral Quiroga2015-06-114-49/+30
| | | | | | | | | | | The same fix Marius implemented for gen6 (commit a9b04d8a) and gen7 (commit 24ecf37a). Also, we need the same code to handle special cases of line width in gen6, gen7 and now gen8, so put that in the helper function we use to compute the line width. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: do_blit_drawpixels: decode array formatsAlexander Monakov2015-06-111-0/+2
| | | | | | | | | | | | Correct a regression introduced by commit 922c0c9fd526 by converting "array format", if received from _mesa_format_from_format_and_type, to mesa_format. References: https://bugs.freedesktop.org/show_bug.cgi?id=90839 Signed-off-by: Alexander Monakov <[email protected]> Tested-by: AnAkkk <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: do not round line width when multisampling or antialiaing are enabledIago Toral Quiroga2015-06-115-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit fe74fee8fa721a we rounded the line width to the nearest integer to match the GLES3 spec requirements stated in section 13.4.2.1, but that seems to break a dEQP test that renders wide lines in some multisampling scenarios. Ian noted that the Open 4.4 spec has the following similar text: "The actual width of non-antialiased lines is determined by rounding the supplied width to the nearest integer, then clamping it to the implementation-dependent maximum non-antialiased line width." and suggested that when ES removed antialiased lines, they removed "non-antialised" from that paragraph but probably should not have. Going by that note, this patch restricts the quantization implemented in fe74fee8fa721a only to regular aliased lines. This seems to keep the tests fixed with that commit passing while fixing the broken test. v2: - Drop one of the clamps (Ken, Marius) - Add a rule to prevent advertising line widths that when rounded go beyond the limits allowed by the hardware (Ken) - Update comments in the code accordingly (Ian) - Put the code in a utility function (Ian) Fixes: dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90749 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: "10.6" <[email protected]>
* i965: Momentarily pretend to support ARB_texture_stencil8 for blits.Kenneth Graunke2015-06-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Broadwell's stencil blitting code attempts to bind a renderbuffer as a texture, using dd->BindRenderbufferTexImage(). This calls _mesa_init_teximage_fields(), which then attempts to set img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which assert fails if internalFormat is GL_STENCIL_INDEX8 but ARB_texture_stencil8 is unsupported. To work around this, just pretend to support the extension momentarily, during the blit. Meta has already munged a variety of other things in the context (including the API!), so it's not that much worse than what we're already doing. Fixes regressions since commit f7aad9da20b13c98f77d6a690b327716f39c0a47 (mesa/teximage: use correct extension for accept stencil texture.). v2: Add an XXX comment explaining the situation (requested by Jason Ekstrand and Martin Peres), and an assert that we don't support the extension so we remember to remove this hack (requested by Neil Roberts). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* android: export more dirs from libmesa_dri_commonChih-Wei Huang2015-06-091-1/+3
| | | | | | | | The include paths of libmesa_dri_common are also used by modules that need libmesa_dri_common. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen9: Use raw PS invocation count for queriesBen Widawsky2015-06-091-1/+1
| | | | | | | | | | | | Previously the number needed to be divided by 4 to get the proper results. Now the hardware does the right thing. Through experimentation it seems Braswell (CHV) does also need the division by 4. Fixes piglit test: arb_pipeline_statistics_query-frag Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* fs/reg_allocate: Remove the MRF hack helpers from fs_visitorJason Ekstrand2015-06-092-16/+13
| | | | | | | These are helpers that only exist in this one file. No reason to put them in the visitor. Reviewed-by: Neil Roberts <[email protected]>
* i965/fs: Don't let the EOT send message interfere with the MRF hackJason Ekstrand2015-06-092-3/+17
| | | | | | | | | | | | | Previously, we just put the message for the EOT send as high in the file as it would go. This is because the register pre-filling hardware will stop all over the early registers in the file in preparation for the next thread while you're still sending the last message. However, if something happens to spill, then the MRF hack interferes with the EOT send message and, if things aren't scheduled nicely, will stomp on it. Cc: "10.5 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90520 Reviewed-by: Neil Roberts <[email protected]>
* i965/fs: Drop fs_inst::force_uncompressed.Francisco Jerez2015-06-091-1/+0
| | | | | | This is now unused. Saves a whole bit of memory per instruction. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove dead IR construction code from the visitor.Francisco Jerez2015-06-094-439/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_cmod_propagation to the IR builder.Francisco Jerez2015-06-091-52/+50
| | | | | | | v2: Use set_predicate/condmod. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_saturate_propagation to the IR builder.Francisco Jerez2015-06-091-35/+34
| | | | | | v2: Use set_saturate. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR texturing instructions to the IR builder.Francisco Jerez2015-06-092-5/+6
| | | | | | v2: Don't remove assignments of base_ir just yet. Reviewed-by: Matt Turner <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 15:58:46 +0000