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* intel: Fix miptree height alignment for compressed NPOT textures.Eric Anholt2011-06-141-4/+2
| | | | | | This is effectively just "round up when dividing by 4" compared to the previous code. Fixes the broken stripe at the top of fbo-generatemipmap-formats GL_EXT_texture_compression_rgtc.
* intel: Drop dead preinitialization of align_w, align_h.Eric Anholt2011-06-141-1/+1
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* intel: Drop the cpp argument to intel_miptree_create().Eric Anholt2011-06-145-22/+5
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* intel: Calculate compress_byte in intel_miptree_create.Eric Anholt2011-06-145-26/+18
| | | | One less argument and thing to get wrong.
* intel: Use the gl_format to get the base_format for miptree create.Eric Anholt2011-06-145-5/+1
| | | | One less argument to this insanely long function call.
* intel: Drop the internal_format field of the mipmap tree.Eric Anholt2011-06-145-15/+4
| | | | This has been replaced with the gl_format now.
* intel: Make the intel_miptree_match_image format check more specific.Eric Anholt2011-06-142-12/+3
| | | | | | | | We don't care just about the internalFormat/cpp/compressed, but about the specific format chosen. We have no support for format translations as part of texture validation, and furthermore it has restrictions in the GL specification. However, we should be making consistent decisions for this check anyway.
* i915: Drop dead argument to translate_texture_format().Eric Anholt2011-06-142-6/+3
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* intel: Add block alignment for RGTC textures.Eric Anholt2011-06-144-32/+18
| | | | | We were using the default 4x2 alignment instead of the 4x4 required for RGTC textures.
* intel: Add the MESA_FORMAT as a field of the miptree.Eric Anholt2011-06-145-4/+14
| | | | | We only had internal_format before, which is way more irritating to work with.
* intel: Fix 2x2 and 1x1 compressed teximages from _mesa_generate_mipmap()Eric Anholt2011-06-141-5/+12
| | | | | | | | | | Generally image uploads to a the region occur at TexImage time, but that's not the case for fallback _mesa_generate_mipmap(), and in this path we were forgetting to align the width when dividing height. We were just leaving out parts of the compressed block at 2x2 and 1x1 levels. Fixes gen-compressed-teximage.
* intel: Fix mipmap and format handling of blit glCopyPixels().Eric Anholt2011-06-131-45/+53
| | | | Fixes fbo-mipmap-copypix.
* intel: Do the drawable x/y offset in intel_renderbuffer_map() for spans.Eric Anholt2011-06-131-64/+27
| | | | | | | | | | | We were mapping the renderbuffer once, then walking over all the buffers to map just the texture ones using the other texture mapping function that handled the x/y offset to the image in the region. But then we would go and overwrite *those* mappings with the original mappings for depth/stencil, which was wrong. Instead, just walk over the attachments once and map the attachments. Wasn't that easy?
* intel: Use rb->Data and rb->RowStride to handle spans Y flipping.Eric Anholt2011-06-131-7/+4
| | | | | | | | This is already pointing at 0 or Height - 1 and with an appropriate pitch, so no need to recompute those values per customization of the spans code. Cuts 3 out of 21kb of the compiled size. Reviewed-by: Chad Versace <[email protected]>
* intel: Clean up intel_render_texture with a rename and a helper function.Eric Anholt2011-06-131-10/+6
| | | | | | | | | | The "newImage" isn't particularly new -- it might be the same texture that was attached to the same attachment point before. This function also gets called when just rebinding back to an FBO with a texture attachment. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: Move the draw_x/draw_y to the renderbuffer where it belongs.Eric Anholt2011-06-1312-80/+97
| | | | | | | | | | | | | | | | It was originally located in the region because the tracking of depth/color buffers was on the regions, and getting back to the irb would have been tricky. Now, we're keying off of the renderbuffer in more places, which means we can move these fields where they belong. This could fix potential rendering failure with a single texture having multiple images attached to different renderbuffers across shareCtx (as far as I can tell, this was the only failure we could cause, since anything else should trigger intel_render_texture in between, for example a BindFramebuffer). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* dri: include swrast.h, not s_texrender.hBrian Paul2011-06-132-2/+2
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* mesa: move texrender.c to swrastBrian Paul2011-06-132-8/+8
| | | | | | | This stuff is really for software rendering, it's not core Mesa. A small step toward pushing the FetchTexel() stuff down into swrast. Reviewed-by: Eric Anholt <[email protected]>
* i965: Add support for GL_FIXED vertex attributes.Eric Anholt2011-06-104-1/+41
| | | | | | | | | This sadly requires work in the VS to rescale them, because the hardware doesn't support this format natively. Fixes arb_es2_compatibility-fixed-type and gtf/fixed_data_type. Reviewed-by: Ian Romanick <[email protected]>
* Fix format not a string literal error with -Werror=format-securityEugeni Dodonov2011-06-101-1/+1
| | | | | | | A trivial fix for error: format not a string literal and no format arguments with compiling with -Werror=format-security flags. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/brw: Fix emit_depthbuffer() when packed depth/stencil texture is attachedChad Versace2011-06-101-11/+5
| | | | | | | | | | | | | If either depth or stencil buffer has packed depth/stencil format, then do not use separate stencil. Before this commit, emit_depthbuffer() incorrectly assumed that the texture's stencil renderbuffer wrapper was a *separate* stencil buffer, because the depth and stencil renderbuffer wrappers are distinct for depth/stencil textures (that is, depth_irb != stencil_irb). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38134 Signed-off-by: Chad Versace <[email protected]>
* i965/gen6: Add support for gl_PointCoord.Eric Anholt2011-06-091-0/+3
| | | | | | | | | This is just like PointSprite overrides, but it's always on for that attribute. Fixes glsl-fs-pointcoord, gtf/point_sprites. Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Fix point sprite texture coordinate overrides.Eric Anholt2011-06-091-7/+7
| | | | | | | | We were assuming that the input attribute n to the FS was FRAG_ATTRIB_TEXn, which happened to be true often enough for our testcases. Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Refactor SF setup a bit to handle overrides in one place.Eric Anholt2011-06-091-19/+24
| | | | Acked-by: Kenneth Graunke <[email protected]>
* mesa: get rid of homegrown logbase2 implementation in driversRoland Scheidegger2011-06-092-28/+2
| | | | | Some of the logbase2 functions did just the same as _mesa_logbase2, though they were taking signed numbers (but it shouldn't matter for them).
* i965/gen7: Call gen7_create_constant_surface instead of brw_[...].Kenneth Graunke2011-06-083-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes 17 piglit tests: - glsl-vs-arrays-3 - glsl-vs-texturematrix-2 - glsl-vs-uniform-array-2 - arl - nv-arl - nv-init-zero-addr - vp-address-01 - vp-arl-constant-array - vp-arl-constant-array-huge - vp-arl-constant-array-huge-offset - vp-arl-constant-array-huge-offset-neg - vp-arl-constant-array-huge-relative-offset - vp-arl-constant-array-huge-varying - vp-arl-env-array - vp-arl-local-array - vp-arl-neg-array - vp-arl-neg-array-2 Fixes 4 glean tests: - glsl1-constant array of vec4 with variable indexing, vertex shader - glsl1-constant array with variable indexing, vertex shader - glsl1-constant array with variable indexing, vertex shader (2) - vp1-ARL test Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Enable SIMD16 fragment shader dispatch.Kenneth Graunke2011-06-081-2/+6
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Don't emit 3DSTATE_GS_SVB_INDEX on Ivybridge.Kenneth Graunke2011-06-081-7/+9
| | | | | | | | | | According to vol2a.07, it only applies from Cantiga to Sandybridge. I found this in my ringbuffers while investigating various GPU hangs. While it may not have been the cause, it seemed wise to remove it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Program stencil buffers on Ivybridge.Kenneth Graunke2011-06-081-19/+42
| | | | | | | | Thanks to Chad's hard work implementing separate stencil and HiZ support, this is entirely straightforward. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Add a prepare_depthbuffer function.Kenneth Graunke2011-06-081-0/+15
| | | | | | | We need to call add_validated_bo to do proper aperture space accounting. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: gen7_emit_depthbuffer needs the _NEW_DEPTH dirty bit.Kenneth Graunke2011-06-081-1/+2
| | | | | | | For ctx->Depth.Mask. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Remove stencil renderbuffer from gen7_depth_format.Kenneth Graunke2011-06-081-3/+0
| | | | | | | | Since Gen7 doesn't support packed depth/stencil, the stencil buffer can't possibly be relevant for determining the depth format. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Request DRI2 buffers for separate stencil and hizChad Versace2011-06-083-14/+444
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When it is sensible to do so, 1) intelCreateBuffer() now attaches separate depth and stencil buffers to the framebuffer it creates. 2) intel_update_renderbuffers() requests for the framebuffer a separate stencil buffer (DRI2BufferStencil). The criteria for "sensible" is: - The GLX config has nonzero depth and stencil bits. - The hardware supports separate stencil. - The X driver supports separate stencil, or its support has not yet been determined. If the hardware supports hiz too, then intel_update_renderbuffers() also requests DRI2BufferHiz. If after requesting DRI2BufferStencil we determine that X driver did not actually support separate stencil, we clean up the mistake and never ask for DRI2BufferStencil again. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add assertions to intelCreateBuffer()Chad Versace2011-06-081-3/+12
| | | | | | | | | | | | | | | Assert that the GLX config has an expected depth/stencil bit combination: one of d24/s8, d16/s0, d0/s0. These are the only depth/stencil configurations that we advertise. Remove the check for software stencil, because given the assertions' constraints the check always fails. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Refactor intel_update_renderbuffers()Chad Versace2011-06-081-111/+212
| | | | | | | | | | | | | | | | | | | | | | Extract the code that queries DRI2 to obtain the DRIdrawable's buffers into intel_query_dri2_buffers_no_separate_stencil(). Extract the code that assigns the DRI buffer's DRM region to the corresponding renderbuffer into intel_process_dri2_buffer_no_separate_stencil(). Rationale --------- The next commit enables intel_update_renderbuffers() to query for separate stencil and hiz buffers. Without separating the separate-stencil and no-separate-stencil paths, intel_update_renderbuffers() degenerates into an impenetrable labyrinth of if-trees. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add function intel_renderbuffer_set_hiz_region()Chad Versace2011-06-082-0/+17
| | | | | | | | | | | It's the analog of intel_renderbuffer_set_region(), but for the hiz region of course. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel/intel_context.c: Remove unused functionsChad Versace2011-06-081-48/+0
| | | | | | | | | | | Remove functions intel_override_hiz() and intel_override_separate_stencil(). They are now located in intel_screen.c. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add flags to intel_screen for hiz and separate stencilChad Versace2011-06-083-7/+73
| | | | | | | | | | | | | | | | | | | | | Add the fields below to intel_screen. The expression in parens is the value to which intelInitScreen2() currently sets the field. GLboolean hw_has_separate_stencil (true iff gen >= 7) GLboolean hw_must_use_separate_stencil (true iff gen >= 7) GLboolean hw_has_hiz (always false) enum intel_dri2_has_hiz dri2_has_hiz (INTEL_DRI2_HAS_HIZ_UNKNOWN) The analogous fields in intel_context now inherit their values from intel_screen. When hiz and separate stencil become completely implemented for a given chipset, then the respective fields need to be enabled. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Define enum intel_dri2_has_hizChad Versace2011-06-081-0/+56
| | | | | | | | | | | | | ... which indicates if the X driver supports DRI2BufferHiz and DRI2BufferStencil. I'm placing this in its own commit due to the large comment block. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Define span functions for S8 renderbuffersChad Versace2011-06-081-0/+64
| | | | | | | | | Since the stencil buffer is interleaved, the generic Mesa renderbuffer accessors do not suffice. Custom span functions are necessary. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/brw: Emit state for hiz and separate stencil buffersChad Versace2011-06-082-9/+107
| | | | | | | | | | When emitting 3DSTATE_DEPTH_BUFFER, also emit 3DSTATE_HIER_DEPTH_BUFFER if there is a hiz buffer. Ditto for 3DSTATE_STENCIL_BUFFER and a separate stencil buffer. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* mga: enable GL_ARB_vertex_array_object extensionNicolas Kaiser2011-06-071-0/+2
| | | | | | | Tested on a Matrox G550 AGP. Signed-off-by: Nicolas Kaiser <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* intel: Update intel-decode.c from intel-gpu-tools.Eric Anholt2011-06-072-88/+785
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* intel: Implement glFinish() correctly by waiting on all previous rendering.Eric Anholt2011-06-073-16/+13
| | | | | Before, we were waiting for (most of) the current framebuffer to be done, which is not quite the same thing.
* radeon: Use pciid list to generate PCI_CHIP_<FAMILY>_<ID> definesBenjamin Franzke2011-06-071-491/+9
| | | | Reviewed-by: Alex Deucher <[email protected]>
* i965: Fix flipped GT1 vs GT2 URB VS entry count limits.Eric Anholt2011-06-071-2/+2
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* i965: Update SURFACE_STATE dumping for Ivybridge.Kenneth Graunke2011-06-061-3/+43
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Update SAMPLER_STATE dumping for Ivybridge.Kenneth Graunke2011-06-061-1/+53
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Update SF_CLIP_VIEWPORT state dumping for Ivybridge.Kenneth Graunke2011-06-061-2/+38
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* dri/nouveau: fix gnome-shell segfaultBen Skeggs2011-06-061-1/+1
| | | | Signed-off-by: Ben Skeggs <[email protected]>
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