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* intel: Mark the FBO as incomplete if there's no intel_renderbuffer for it.Eric Anholt2009-09-211-0/+5
| | | | | | | This happens to rendering with textures with a border, which had resulted in a segfault on dereferencing the irb. (cherry-picked from commit 8bba183b9eeb162661a287bf2e118c6dd419dd24)
* intel: Fix crash in intel_flush().Michel Dänzer2009-09-211-1/+2
| | | | | | Since commit 2921a2555d0a76fa649b23c31e3264bbc78b2ff5 ('intel: Deassociated drawables from private context struct in intelUnbindContext'), intel->driDrawable may be NULL in intel_flush().
* intel: Deassociated drawables from private context struct in intelUnbindContextIan Romanick2009-09-161-0/+8
| | | | | | | | | | | | The generic DRI infrastructure makes sure that __DRIcontextRec::driDrawablePriv and __DRIcontextRec::driReadablePriv are set to NULL after unbinding a context. However, the intel_context structure keeps cached copies of these pointers. If these cached pointers are not NULLed and the drawable is actually destroyed after unbinding the context (typically by way of glXDestroyWindow), freed memory will be dereferenced in intelDestroyContext. This should fix bug #23418.
* intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
| | | | | | | | | Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
* i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
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* i965: Fix warnings in intel_pixel_read.c.Eric Anholt2009-09-041-0/+4
| | | | (cherry picked from commit c80ce5ac90b1e0ac7a72cd41c314aa2000bfecf5)
* intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-044-1/+29
| | | | (cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
* intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-043-3/+13
| | | | | | We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue. (cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
* intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-09-042-306/+307
| | | | (cherry picked from commit dcfe0d66bfff9a55741aee298b7ffb051a48f0d3)
* i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| | | | (cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)
* intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| | | | | (cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
* intel: Align untiled region height to 2 according to 965 docs.Eric Anholt2009-09-041-0/+7
| | | | | | This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
* i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| | | | | | | | | For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. (cherry picked from commit f44916414ecd2b888c8a680d56b7467ccdff6886)
* i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
| | | | | | | | | Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992 (cherry picked from commit 78c022acd0b37bf8b32f04313d76255255e769c1) (cherry picked from commit 63d7a2f53fb38e170f4e55f2b599e918edf2c512)
* i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
| | | | (cherry picked from commit fd7d764514c540987549c3ea88a2d669b0f0ea58)
* i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-09-041-0/+13
| | | | | | Previously, we'd be branching based on whatever condition code happened to be laying around. (cherry picked from commit 7007f8b352763af89805f287153cb7972bff0523)
* i965: Spell "conditional" correctly.Eric Anholt2009-09-043-15/+15
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* i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-09-041-1/+5
| | | | | Bug #20821 (cherry picked from commit 191e028de20b2f954621b652aa77b06d0e93652a)
* i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-09-041-0/+14
| | | | | | | | | | | This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911. (cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
* i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
| | | | | | | See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945. (cherry picked from commit e340d4f9866db4bae391288e83a630a310b0dd2b)
* i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-09-041-1/+8
| | | | | | | This fix is just from code and docs inspection, but it may fix hangs on some applications. (cherry picked from commit e93848e595176ae0bad3bfe64e0ca63fd089bb72)
* i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-09-041-0/+22
| | | | | | | | | | It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS) (cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
* i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-09-042-29/+18
| | | | | The code duplication bothered me. (cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
* i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-09-041-1/+1
| | | | | It's the last addressable byte, not the byte after the end of the buffer. (cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
* i965: rename var: s/tmp/vs_inputs/Brian Paul2009-09-041-8/+8
| | | | (cherry picked from commit 840c09fc71542fdfc71edd2a2802925d467567bb)
* dri: Fix problems with unitialized values in dri screen object.Pauli Nieminen2009-08-071-1/+1
| | | | | | This fixes crash in r200 KMS driver when pSAREA was set to 1 randomly because of memory wasn't cleared. Signed-off-by: Pauli Nieminen <[email protected]>
* intel: Fix inverted test for disabling flushing of front buffer output.Brian Paul2009-08-041-1/+1
| | | | | | | | | | The comment disagreed with the code, and nicely drew my eyes to what was going wrong. Bug #21774 (blender) Bug #21788 (readpix) (cherry picked from master, commit fd65418f600874b05f902b622078b40bc1abb24a)
* intel: Wait on the last swapbuffers to complete before queuing a new one.Brian Paul2009-08-043-0/+28
| | | | | | | | | | | | | This fixes jerkiness in doom3 and other apps since the kernel change to throttle less absurdly, which led to a thundering herd of frames. Because this is a rather minimal fix, there is at least one downside: If the whole scene completes in one batchbuffer, we'll end up stalling the GPU. Thanks to Michel Dänzer for suggesting using glFlush to signal frame end instead of going to all the effort of adding a new DRI2 extension. (cherry picked from master, commit 0828579a658af01a64b5e699175dc9bbbedcd685)
* intel: Fix leak of DRI option info due to using the wrong free routine.Brian Paul2009-07-271-1/+1
| | | | (cherry picked from commit 6d66f23c50ebe8f973757b6fd1b81c9b7920c447)
* intel: Clean up leak of driver context structure on context destroy.Brian Paul2009-07-271-0/+3
| | | | (cherry picked from commit ddef7dc87b2001fbe117ee5f24a0c645ee95a03c)
* intel: Use _mesa_warning() to report GEM warningsBrian Paul2009-07-271-3/+3
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* intel: Fall back on glBitmap with fog enabled.Eric Anholt2009-07-201-0/+6
| | | | | | | | We would have to build the program with the appropriate fog mode, and also supply the fog coordinate if appropriate. Bug #19413. (cherry picked from commit 8ae02a3919bf31bd33f86208472e100eedb58497)
* i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled.Eric Anholt2009-07-201-1/+2
| | | | | | | Fixes everything-black with meta_clear_tris on quake4-mpdemo and doom3-demo. Bug #18844, 22077. (cherry picked from commit 81d555068408d4343d7627c8bedda5675f09bd21)
* radeon: With DRI1, if we have HW stencil, only expose fbconfigs with stencil.Michel Dänzer2009-07-201-2/+2
| | | | | | | | | | | | Otherwise simple apps like glxgears pick up a DirectColor visual since the X server mixes the depth 32 visual in with the other GLX visuals, and this seems to result in a (mostly) black screen due to a bad ColorMap for a lot of people. The bad ColorMap may be a bug in the apps, the X server or X driver, and regardless of that I think the X server should ideally make the depth 32 GLX visual separate from the rest again, but in the meantime this makes us cope. (depth_bits is either 16 or 24, never 0)
* r128: fix two-sided lighting segfault seen in GLUT's olight demoPeteri Andras2009-07-133-2/+7
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* intel: Bump driver data, add RC3 tagintel_2009q2_rc3Ian Romanick2009-07-121-1/+1
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* i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-07-044-17/+16
| | | | | | | | | | | | the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
* i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt2009-07-041-13/+11
| | | | | | | Thanks to branching, the state of c->current_const[i].index at the point of emitting constant loads for this instruction may not match the actual constant currently loaded in the reg at runtime. Fixes a regression in my GLSL program for idr's class since b58b3a786aa38dcc9d72144c2cc691151e46e3d5.
* intel: Also update stencil bits in intel_update_wrapper().Michel Dänzer2009-07-031-0/+1
| | | | | Fixes assertion failure when binding depth/stencil texture to FBO stencil attachment.
* i915: Fix assertion failure on remapping a non-BO-backed VBO.Eric Anholt2009-06-301-1/+4
| | | | | | Failure to set the obj->Pointer back to null tripped up the assertion. Bug #22428. (cherry picked from commit 57a06d3a48c9af1067ec05e3ad96c58f4b9b99be)
* intel: added null ptr checkBrian Paul2009-06-291-1/+1
| | | | This fixes a segfault seen with piglit's fdo20701 test.
* intel / DRI2: Additional flush of fake front-buffer to real front-bufferIan Romanick2009-06-261-0/+11
| | | | | | | | | | | To maintain correctness, the server will copy the real front-buffer to a newly allocated fake front-buffer in DRI2GetBuffersWithFormat. However, if the DRI2GetBuffersWithFormat is triggered by glViewport, this will copy stale data into the new buffer. Fix this by flushing the current fake front-buffer to the real front-buffer in intel_viewport. Fixes bug #22288.
* i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-221-0/+1
| | | | | | | glsl compiler will not generate OPCODE_SWZ, and as a first step it would be translated away to a MOV anyway (why?), but later internally this opcode is generated (for EXT_texture_swizzling). (cherry picked from commit 4ef1f8e3b52a06fcf58f78c9c36738531b91dbac)
* intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL.Michel Dänzer2009-06-221-1/+1
| | | | | Fixes glean depthStencil test. (cherry picked from commit 3885b708fdbb7bbd5dd3a247c41fb9a75ee7c057)
* i965: added intelFlush() call in intel_get_tex_image()Brian Paul2009-06-221-0/+6
| | | | | Fixes the render-to-texture test in progs/tests/getteximage.c (cherry picked from commit a03b349153660e449daf4f56d750f1caef23b1a5)
* intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.Eric Anholt2009-06-192-3/+3
| | | | | | Fixes oglconform zbfunc.c and pxtrans-cidraw.c, at least. (cherry picked from commit 405300bb190f516e16b704050abe3389b366ed27)
* intel: Fix glClear behavior versus display lists.Eric Anholt2009-06-191-1/+1
| | | | | | | The CALL_DrawArrays was leaking the clear's primitives into the display list with GL_COMPILE_AND_EXECUTE. Use _mesa_DrawArrays instead, which doesn't appear to leak. Fixes piglit dlist-clear test. (cherry picked from commit 64edde1004f7a69e77877bba24d315a92bcd47c8)
* radeons: use dp4 for position invariant vertex programsRoland Scheidegger2009-06-193-0/+6
| | | | | | | | Fixes #22181. R200 requires this since DP4 is used in hw tnl mode. R300 prefers it (should be faster due to no instruction dependencies), but both methods should be correct (when sw tcl is used though, MUL/MAD might be faster). Probably doesn't make much difference for R100 since vertex progs are executed in software anyway, but let's just keep it the same there too.
* intel: remove extra \n from warning stringBrian Paul2009-06-171-1/+1
| | | | (cherry picked from commit 42e9bde0fa2276b8f5bb434328eea7665794b127)
* i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-06-171-0/+10
| | | | | | | | | | | | | | | With 1D textures, GL_TEXTURE_WRAP_T should be ignored (only GL_TEXTURE_WRAP_S should be respected). But the i965 hardware seems to follow the value of GL_TEXTURE_WRAP_T even when sampling 1D textures. This fix forces GL_TEXTURE_WRAP_T to be GL_REPEAT whenever 1D textures are used; this allows the texture to be sampled correctly, avoiding "imaginary" border elements in the T direction. This bug was demonstrated in the Piglit tex1d-2dborder test. With this fix, that test passes. (cherry picked from commit ab6c4fa582972e25f8800c77b5dd5b3a83afc996)
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