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* intel: Avoid mapping the texture image for CopyTex{,Sub}ImageAdam Jackson2009-03-301-11/+13
| | | | | | We don't upload the pixels with the CPU in that case, so the map will only serve as a way of triggering cache flushes over a bunch of data we don't touch.
* i965: srgb texture fixesRoland Scheidegger2009-03-283-10/+27
| | | | | | | | i965 can either do SRGBA8_REV format or SARGB8 format, but not SRGBA8. Could add SRGBA8_REV support to mesa, but simply use SARGB8 for now. While here, also add true srgb luminance / luminance_alpha support - unfortunately the published docs fail to mention which asics support this, tested on g43 so assume this works on any g4x.
* i965: add support for signed rgba texture formatRoland Scheidegger2009-03-283-0/+9
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* fix various small intel blitter issuesRoland Scheidegger2009-03-281-11/+12
| | | | | | use color format constants instead of magic numbers remove handling of cpp 0 or 3 (neither is possible) in various places don't misconfigure 8 bit surface blits as rgb565
* r300: cleanup swtcl a littleMaciej Cencora2009-03-251-9/+1
| | | | | | - remove disabled code - silence compiler warnings (uinitialized values) - remove unneeded code
* Convert u_int*_t to C99 standard uint*_tAlan Coopersmith2009-03-251-1/+1
| | | | Signed-off-by: Alan Coopersmith <[email protected]>
* r300_cmdbuf.c: convert cast to a form supported by Sun ccAlan Coopersmith2009-03-251-1/+1
| | | | | | | Fixes Sun cc error: "r300_cmdbuf.c", line 142: invalid cast expression Signed-off-by: Alan Coopersmith <[email protected]>
* r300: Texture size limit cleanups.Michel Dänzer2009-03-254-6/+23
| | | | | | | | | Since core Mesa MAX_TEXTURE_LEVELS was bumped, we were incorrectly advertising a maximum texture size of 4096 on older chips, causing corrupted menu text in Extreme Tux Racer or Armagetron. Also make sure our texture image array can actually hold all the mipmap levels we support...
* i965: fix point rasterization when rendering to FBORobert Ellison2009-03-242-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | The FBO pixel coordinate system, with (0,0) as the upper-left pixel, is inverted in Y compared to the normal OpenGL pixel coordinate system, which has (0,0) as its lower-left pixel. Viewport and polygon stipple are sensitive to this inversion; so is point rasterization. The basic fix is simple: when rendering to an FBO, instead of the normal RASTRULE_UPPER_RIGHT that's appropriate for OpenGL windows, use the Y inversion RASTRULE_LOWER_RIGHT. Unfortunately, current Intel documentation has this value listed as "Reserved, but not seen as useful". It does work on at least some i965-class devices, though; and the worst that could happen if an older device didn't support it would be incorrect point rasterization to FBOs, which is what happens already, so this fix is at least no worse than what happens presently, and is better for some (and possibly all) i965-class devices.
* i965: Fix glFrontFacing in twoside GLSL demo.Eric Anholt2009-03-238-38/+79
| | | | | | | This also cuts instructions by just using the existing bit in the payload rather than computing it from the determinant in the SF unit and passing it as a varying down to the WM. Something still goes wrong with getting the backface color right, but a simpler shader appears to get the right result.
* i965: Fix fog coordinate g,b,a values when glFrontFacing isn't used.Eric Anholt2009-03-231-0/+50
| | | | | | | | | Previously, we would sample (f,glFrontFacing,undef,undef) instead of the (f,0,0,1) that fragment.fogcoord is supposed to return. Due to glFrontFacing's presence in FOGC.y, we'll still give bad results there when glFrontFacing is used. Bug #19122, piglit testcase fp-fog.
* i965: Clean up a bit of mess with unneeded variables in emit_interp.Eric Anholt2009-03-231-7/+2
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* i965: Fix trailing "d" in debug output for 3DSTATE_VERTEX_ELEMENTS.Eric Anholt2009-03-231-1/+1
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* i965: Fix occlusion query when no other WM state updates occur.Eric Anholt2009-03-231-2/+3
| | | | | | | | | Turns out that XXX comment was important. We weren't flagging the WM to re-update with the statistics enable, so we got zeroes out of our query. Bug #20740, fixes piglit occlusion_query test. Signed-off-by: Eric Anholt <[email protected]>
* Fix DRI2 accelerated EXT_texture_from_pixmap with GL_RGB format.Eric Anholt2009-03-206-15/+51
| | | | | | | | | | | | | | This requires upgrading the interface so that the argument to glXBindTexImageEXT isn't just dropped on the floor. Note that this only fixes the accelerated path on Intel, as Mesa's texture format support is missing x8r8g8b8 support (right now, GL_RGB textures get uploaded as a8r8gb8, but in this case we're not doing the upload so we can't really work around it that way). Fixes bugs with compositors trying to use shaders that use alpha channels, on windows without a valid alpha channel. Bug #19910 and likely others as well. Reviewed-by: Ian Romanick <[email protected]>
* i965: more register number assertionsmesa_20090313Brian Paul2009-03-131-0/+7
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* i965: add some register number assertionsBrian Paul2009-03-131-0/+8
| | | | | Haven't seen failures yet, but if/when there are, more investigation will be done.
* i965: remove unused PROGRAM_INTERNAL_PARAM, added commentBrian Paul2009-03-131-3/+1
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* i965: move declarations before codeBrian Paul2009-03-131-6/+6
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* i965: debug code, use gl_register_file typeBrian Paul2009-03-131-1/+7
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* i965: move declaration before codeBrian Paul2009-03-121-2/+1
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* i965: fix const correctnessBrian Paul2009-03-121-1/+1
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* i915: move declarations before codeBrian Paul2009-03-122-4/+4
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* i965: commentsBrian Paul2009-03-121-0/+3
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* i965: fix polygon stipple when rendering to FBORobert Ellison2009-03-121-4/+31
| | | | | | | | | | | | | | | The polygon stipple pattern, like the viewport and the polygon face orientation, must be inverted on the i965 when rendering to a FBO (which itself has an inverted pixel coordinate system compared to raw Mesa). In addition, the polygon stipple offset, which orients the stipple to the window system, disappears when rendering to an FBO (because the window system offset doesn't apply, and there's no associated FBO offset). With these fixes, the conform triangle and polygon stipple tests pass when rendering to texture.
* i965: add support for ATI_envmap_bumpmapRoland Scheidegger2009-03-123-0/+9
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* regenerate glapiRoland Scheidegger2009-03-121-0/+38
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* i965: fix polygon face orientation when rendering to FBORobert Ellison2009-03-111-2/+8
| | | | | | | | | | | | | | In the i965, the FBO coordinate system is inverted from the standard OpenGL/Mesa coordinate system; that means that the viewport and the polygon face orientation have to be inverted if rendering to a FBO. The viewport was already being handled correctly; but polygon face was not. This caused a conform failure when rendering to texture with two-sided lighting enabled. This fixes the problem in the i965 driver, and adds to the comment about the gl_framebuffer "Name" field so that this isn't a surprise to other driver writers.
* intel: include main/viewport.hBrian Paul2009-03-111-0/+1
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* i965: fix lock-ups when GLSL program wrote to gl_FragDepthBrian Paul2009-03-111-1/+27
| | | | | | | It seems the code that set up the FB_WRITE message was incomplete in this case. The number of payload registers was wrong and that caused a hang. It would be good to have a second set of eyes take a look at this...
* i965: more code clean-ups, commentsBrian Paul2009-03-101-4/+11
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* i965: minor code clean-ups, commentsBrian Paul2009-03-101-10/+12
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* i965: use new cast wrappersBrian Paul2009-03-103-9/+16
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* i965: added cast wrappers, commentsBrian Paul2009-03-101-3/+29
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* i965: asst. code clean-ups, commentsBrian Paul2009-03-101-17/+19
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* i965: fix typos in commentsBrian Paul2009-03-101-2/+2
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* i965: fix cube map lock-up / corruptionBrian Paul2009-03-091-9/+13
| | | | | | If we're using anything but GL_NEAREST sampling of a cube map, we need to use the BRW_TEXCOORDMODE_CUBE texcoord wrap mode. Before this, the GPU would either lock up or subsequent texture filtering would be corrupted.
* fix typo in fragment pipe alu define, should fix dot3_rgb tex combineRoland Scheidegger2009-03-091-1/+1
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* r300: remove assignment to removed StringPos fieldBrian Paul2009-03-071-1/+0
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* mesa: move glViewport and glDepthRange functions into new viewport.c fileBrian Paul2009-03-072-1/+3
| | | | A bit of refactoring with an eye toward ES2 and GL 3.1
* mesa: gl_register_file enum typedefBrian Paul2009-03-072-3/+3
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* mesa: remove GL_MESA_program_debug extensionBrian Paul2009-03-071-4/+0
| | | | This was never fully fleshed out and hasn't been used.
* mesa: remove last of _mesa_unreference_framebuffer() callsBrian Paul2009-03-0716-16/+16
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* r300: shut up valgrindMaciej Cencora2009-03-072-2/+2
| | | | | | It complained about uninitialized values Signed-off-by: Nicolai Haehnle <[email protected]>
* i965: check if we run out of GRF/temp registersBrian Paul2009-03-061-1/+25
| | | | | | | Before this change we would up emitting instructions with invalid register numbers. This typically (but not always) hung the GPU. For now, just prevent emitting bad instructions to avoid hangs. Still need to do some kind of proper error recovery.
* i965: bump up BRW_EU_MAX_INSNBrian Paul2009-03-061-1/+1
| | | | This is the size of the intermediate instruction buffer.
* i965: commentsBrian Paul2009-03-061-0/+2
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* i965: comments and minor clean-upsBrian Paul2009-03-061-3/+43
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* i965: avoid unnecessary calls to brw_wm_is_glsl()Brian Paul2009-03-064-2/+12
| | | | | | | | | This function scans the shader to see if it has any GLSL features like conditionals and loops. Calling this during state validation is expensive. Just call it when the shader is given to the driver and save the result. There's some new/temporary assertions to be sure we don't get out of sync on this.
* r300: fix depth write regression (found by Nicolai Haehnle)Maciej Cencora2009-03-061-3/+10
| | | | Signed-off-by: Nicolai Haehnle <[email protected]>
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