Commit message (Collapse) | Author | Age | Files | Lines | |
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* | radeon space: realign with drm space check code | Dave Airlie | 2009-08-15 | 1 | -1/+1 |
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* | r300: fixup space checks since VBO code | Dave Airlie | 2009-08-15 | 1 | -16/+9 |
| | | | | Hopefully this gets the ordering correct so the space checks don't fail. | ||||
* | r300: add just in case warn I don't think this can actually happen | Dave Airlie | 2009-08-15 | 1 | -0/+5 |
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* | radeon: enable vertex splitting for IBs | Dave Airlie | 2009-08-15 | 2 | -13/+47 |
| | | | | | | Based on Maciej's code, just fixed up the alignments for INDX_BUFFER ut2004 runs AS-Convoy | ||||
* | i965: disable bounds checking on arrays with stride 0 | Roland Scheidegger | 2009-08-15 | 1 | -1/+1 |
| | | | | | | | | if stride is 0 we cannot use count as max index for bounds checking, since the hardware will simply return 0 as data for indices failing bounds check. If stride is 0 any index should be valid hence simply disable bounds checking in this case. This fixes bugs introduced with e643bc5fc7afb563028f5a089ca5e38172af41a8. | ||||
* | i965: Add support for GL_ARB_seamless_cube_map | Ian Romanick | 2009-08-14 | 2 | -17/+28 |
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* | Merge branch 'vbo_clean' | Maciej Cencora | 2009-08-15 | 13 | -334/+621 |
|\ | | | | | | | | | Conflicts: src/mesa/drivers/dri/r300/r300_draw.c | ||||
| * | r300: mark VBO buffer objects as persistent | Maciej Cencora | 2009-08-15 | 1 | -3/+6 |
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| * | r300: unmap buffer objects after usage | Maciej Cencora | 2009-08-14 | 1 | -1/+11 |
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| * | r300: remove broken vertex splitting | Maciej Cencora | 2009-08-14 | 2 | -13/+5 |
| | | | | | | | | Revert to previous behaviour of dropping to big render operations. | ||||
| * | r300: rework index buffer setup | Maciej Cencora | 2009-08-14 | 3 | -119/+126 |
| | | | | | | | | Copy elements directly to DMA bo to get rid of one memcpy, and prepare for using VBOs for index buffer. | ||||
| * | r300: remove unused software TNL path | Maciej Cencora | 2009-08-14 | 4 | -118/+6 |
| | | | | | | | | This doesn't remove software TCL path - so RS480 and RS690 work as before. | ||||
| * | r300: use VBOs for vertex attributes | Maciej Cencora | 2009-08-14 | 3 | -84/+187 |
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| * | r300: add required symlinks | Maciej Cencora | 2009-08-14 | 2 | -0/+2 |
| | | | | | | | | Reported by adamk on #radeon | ||||
| * | radeon: handle debug versions of radeon_bo_open | Maciej Cencora | 2009-08-14 | 1 | -1/+10 |
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| * | radeon: add VBO support (not enabled yet) | Maciej Cencora | 2009-08-14 | 3 | -1/+271 |
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| * | radeon: export emitvec* functions | Maciej Cencora | 2009-08-14 | 2 | -2/+4 |
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| * | radeon: constify some parameters | Maciej Cencora | 2009-08-14 | 2 | -8/+8 |
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* | | intel: in intel_context struct use typedef for sarea struct | Tobias Doerffel | 2009-08-14 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | Using drm_i915_sarea_t instead of struct drm_i915_sarea seems to be a common standard now, therefore fix it also in intel_context structure. Additionally this silences a compiler warning: intel_swapbuffers.c: In function `intelFixupVblank': intel_swapbuffers.c:48: warning: initialization from incompatible pointer type Signed-off-by: Tobias Doerffel <[email protected]> | ||||
* | | r600: emit SURFACE_BASE_UPDATE on depth base updates on rv6xx | Alex Deucher | 2009-08-14 | 1 | -0/+8 |
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* | | r600: move non-surface related cb state to general state | Alex Deucher | 2009-08-13 | 1 | -6/+12 |
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* | | r600: move non-surface related depth state to general state | Alex Deucher | 2009-08-13 | 1 | -23/+15 |
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* | | i965: fix cube map on IGDNG | Xiang, Haihao | 2009-08-13 | 1 | -5/+8 |
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* | | Merge branch 'new-frag-attribs' | Brian Paul | 2009-08-12 | 1 | -27/+34 |
|\ \ | | | | | | | | | | | | | | | | | | | This branch introduces new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputs for GLSL gl_FrontFacing and gl_PointCoord. Before, these attributes were packed with the FOG attribute. That made things complicated elsewhere. | ||||
| * | | mesa: add new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputs | Brian Paul | 2009-07-29 | 1 | -27/+34 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the FOGC attribute contained the fragment fog coord, front/back- face flag and the gl_PointCoord.xy values. Now each of those things are separate fragment program attributes. This simplifies quite a few things in Mesa and gallium. Need to test i965 driver and fix up point coord handling in the gallium/draw module... | ||||
* | | | i965: Make the cube mapping RCP use a writemask. | Eric Anholt | 2009-08-12 | 1 | -2/+2 |
| | | | | | | | | | | | | Fixes cube mapping since the scalar changes. | ||||
* | | | i965: Allocate destination registers for GLSL TEX instructions contiguously. | Eric Anholt | 2009-08-12 | 1 | -0/+24 |
| | | | | | | | | | | | | | | | | | | This matches brw_wm_pass*.c behavior, and fixes the norsetto shadow demo. Bug #19489 | ||||
* | | | i965: drop dead scalar handling in GLSL. | Eric Anholt | 2009-08-12 | 2 | -14/+0 |
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* | | | i965: Correct brw_wm_nr_args for WM_DELTAXY and WM_PIXELXY. | Eric Anholt | 2009-08-12 | 1 | -2/+2 |
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* | | | i965: Drop GLSL ABS code, which is translated away in brw_wm_fp. | Eric Anholt | 2009-08-12 | 1 | -20/+0 |
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* | | | i965: Drop code for emitting OPCODE_SUB, since brw_wm_fp.c makes it an ADD. | Eric Anholt | 2009-08-12 | 1 | -21/+0 |
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* | | | i965: Store the dispatch width in the WM compile struct. | Eric Anholt | 2009-08-12 | 2 | -0/+3 |
| | | | | | | | | | | | | I'll be using this in merging brw_wm_emit.c and brw_wm_glsl.c | ||||
* | | | i965: Handle scalar result swizzling in shared GLSL/non-GLSL code. | Eric Anholt | 2009-08-12 | 5 | -69/+103 |
| | | | | | | | | | | | | | | | This is preparation for merging of brw_wm_glsl.c and brw_wm_emit.c, and glsl.c doesn't swizzle channel results around. | ||||
* | | | i965: Flag ARL-using programs as requiring brw_wm_glsl.c | Eric Anholt | 2009-08-12 | 1 | -0/+1 |
| | | | | | | | | | | | | This doesn't fix the glean testcase, but I guess it provides hope. | ||||
* | | | i965: Remove some unused WM opcode args. | Eric Anholt | 2009-08-12 | 1 | -6/+4 |
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* | | | i965: Avoid re-uploading the index buffer when we don't need to. | Eric Anholt | 2009-08-12 | 5 | -16/+55 |
| | | | | | | | | | | | | No performance difference proven at 95% confidence with my GLSL demo (n=10). | ||||
* | | | r600: fix warning | Alex Deucher | 2009-08-12 | 2 | -3/+3 |
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* | | | r600: state cleanups | Alex Deucher | 2009-08-12 | 4 | -52/+40 |
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* | | | r600: clean up Create/DestroyContext | Alex Deucher | 2009-08-12 | 3 | -15/+6 |
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* | | | r200: Prevent TexGenMatrix from leaking when destroying r200 context. | Pauli Nieminen | 2009-08-12 | 2 | -5/+17 |
| | | | | | | | | | | | | Signed-off-by: Pauli Nieminen <[email protected]> | ||||
* | | | vbo: Avoid extra validation of DrawElements. | Eric Anholt | 2009-08-12 | 3 | -38/+23 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This saves mapping the index buffer to get a bounds on the indices that drivers just drop on the floor in the VBO case (cache win), saves a bonus walk of the indices in the CheckArrayBounds case, and other miscellaneous validation. On intel it's a particularly a large win (50-100% in my app) because even though we let the indices stay in both CPU and GPU caches, we still end up waiting for the GPU to be done with the buffer before reading from it. Drivers that want the min/max_index fields must now check index_bounds_valid and use vbo_get_minmax_index before using them. | ||||
* | | | radeon: Minor warnings cleanup. | Eric Anholt | 2009-08-12 | 5 | -7/+16 |
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* | | | i965: Use _MaxElement instead of index-calculated min/max for VBO bounds. | Eric Anholt | 2009-08-12 | 1 | -2/+3 |
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* | | | radeon: Add protection against recursive DRM locking. | Pauli Nieminen | 2009-08-12 | 4 | -3/+64 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reference counting protects DRM lock call from recursive locking that would cause hang. Code also adds optional debugging output for recursive call that is compiled only if NDEBUG is not defined. This code is not 100% thread safe because mesa doesn't include increment and test atomic operation. There is built-in gcc functions but they are only available from gcc 4.2. | ||||
* | | | r600: A shader is bound that exports Z as a float into Red channel | Cooper Yuan | 2009-08-12 | 2 | -0/+4 |
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* | | | r600: use the drm ioctls for swap and texture upload | Alex Deucher | 2009-08-11 | 2 | -31/+27 |
| | | | | | | | | | | | | NOTE: THIS REQUIRES AN UPDATED DRM! | ||||
* | | | mesa/glapi: regenerated files from gl_API.xml | Brian Paul | 2009-08-11 | 1 | -15/+59 |
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* | | | r600: update num of interp if posizition is used | Cooper Yuan | 2009-08-11 | 1 | -8/+10 |
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* | | | intel: use new _mesa_meta_copy_pixels() function | Brian Paul | 2009-08-10 | 1 | -165/+2 |
| | | | | | | | | | | | | glCopyPixels() no longer hits a software fallback when zooming, blending, etc. | ||||
* | | | intel: add missing \n to fprintf() | Brian Paul | 2009-08-10 | 1 | -1/+1 |
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