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* mesa: Optionally build a dricore support library (v3)Christopher James Halse Rogers2011-02-111-7/+5
| | | | | | | | | | | | | | | | | This an adds --enable-shared-dricore option to configure. When enabled, DRI modules will link against a shared copy of the common mesa routines rather than statically linking these. This saves about 30MB on disc with a full complement of classic DRI drivers. v2: Only enable with a gcc-compatible compiler that handles rpath Handle DRI_CFLAGS without filter-out magic Build shared libraries with the full mklib voodoo Fix typos v3: Resolve conflicts with talloc removal patches Signed-off-by: Christopher James Halse Rogers <[email protected]>
* i915: Force lowering of all types of indirect array accesses in the FSIan Romanick2011-02-101-3/+11
| | | | NOTE: This is a candidate for the 7.9 and 7.10 branches.
* i915: Calculate partial result to temp register firstIan Romanick2011-02-101-8/+8
| | | | | | | | | | | | Previously the SNE and SEQ instructions would calculate the partial result to the destination register. This would cause problems if the destination register was also one of the source registers. Fixes piglit tests glsl-fs-any, glsl-fs-struct-equal, glsl-fs-struct-notequal, glsl-fs-vec4-operator-equal, glsl-fs-vec4-operator-notequal. NOTE: This is a candidate for the 7.9 and 7.10 branches.
* r200: add cast to silence warningBrian Paul2011-02-081-1/+1
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* mesa: remove _mesa_create_context_for_api()Brian Paul2011-02-089-9/+9
| | | | Just add the gl_api parameter to _mesa_create_context().
* mesa: remove _mesa_initialize_context_for_api()Brian Paul2011-02-083-4/+5
| | | | Just add the gl_api parameter to _mesa_initialize_context().
* i965: Add missing DEFINE_BITS for brw dirty bits.Kenneth Graunke2011-02-081-0/+4
| | | | | These are only used for debugging, but should be there. Found by inspection.
* i965: Separate the BRW_NEW_(VS|WM)_CONSTBUF dirty bits.Kenneth Graunke2011-02-081-1/+1
| | | | | These were incorrectly defined to the same value - likely due to a cut and paste error. Found by inspection.
* i965: Rename a few more commands to match the documentation.Kenneth Graunke2011-02-082-5/+5
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* i965: Remove pointless keying of WM state on VUE size.Eric Anholt2011-02-081-4/+0
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* intel: Implement dri2::{Allocate,Release}BufferBenjamin Franzke2011-02-071-0/+47
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* Add dri2::{Allocate,Release}Buffer extensionBenjamin Franzke2011-02-072-1/+25
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* r300/compiler: Disable register rename pass on r500Tom Stellard2011-02-051-1/+1
| | | | | | | | | | | The scheduler and the register allocator are not good enough yet to deal with the effects of the register rename pass. This was causing a 50% performance drop in Lightsmark. The pass can be re-enabled once the scheduler and the register allocator are more mature. r300 and r400 still need this pass, because it prevents a lot of shaders from using too many texture indirections. NOTE: This is a candidate for the 7.10 branch.
* r300/compiler: Don't count BEGIN_TEX instructions in the compiler statsTom Stellard2011-02-051-1/+3
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* mesa/965: add support for GL_EXT_framebuffer_sRGB (v2)Dave Airlie2011-02-053-1/+6
| | | | | | | | | | | | This adds i965 support for GL_EXT_framebuffer_sRGB, it introduces a new constant to say that the driver can support sRGB enabled FBOs since enabling the extension doesn't mean the driver can actually support sRGB. Also adds the suggested state flush in the core code suggested by Brian. fix the ARB_fbo color encoding. Signed-off-by: Dave Airlie <[email protected]>
* i965: Drop the dead tracking of color_regions[].Eric Anholt2011-02-043-12/+2
| | | | We pull the draw regions right out of the renderbuffers these days.
* i965: Drop the INTEL_DEBUG=state spam about the cache size check.Eric Anholt2011-02-041-2/+0
| | | | | There's way more interesting info in INTEL_DEBUG=state if you could find it among the state size checks.
* swrast: add an interface createNewContextForAPIHaitao Feng2011-02-032-10/+120
| | | | | | | | This new interface could set up context for OpenGL, OpenGL ES1 and OpenGL ES2. It will be used by egl_dri2 driver. Signed-off-by: Haitao Feng <[email protected]>
* r300c: Unbreak after R4xx support was added to r300/compiler.Michel Dänzer2011-02-032-0/+2
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* r200: remove 0x4243 pci idAlex Deucher2011-02-012-2/+0
| | | | | | | There's no such device. 0x4243 is a pci bridge id, not a GPU. Signed-off-by: Alex Deucher <[email protected]>
* i915: Only mark a register as available if all components are writtenIan Romanick2011-02-011-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously a register would be marked as available if any component was written. This caused shaders such as this: 0: TEX TEMP[0].xyz, INPUT[14].xyyy, texture[0], 2D; 1: MUL TEMP[1], UNIFORM[0], TEMP[0].xxxx; 2: MAD TEMP[2], UNIFORM[1], TEMP[0].yyyy, TEMP[1]; 3: MAD TEMP[1], UNIFORM[2], TEMP[0].zzzz, TEMP[2]; 4: ADD TEMP[0].xyz, TEMP[1].xyzx, UNIFORM[3].xyzx; 5: TEX TEMP[1].w, INPUT[14].xyyy, texture[0], 2D; 6: MOV TEMP[0].w, TEMP[1].wwww; 7: MOV OUTPUT[2], TEMP[0]; 8: END to produce incorrect code such as this: BEGIN DCL S[0] DCL T_TEX0 R[0] = MOV T_TEX0.xyyy U[0] = TEXLD S[0],R[0] R[0].xyz = MOV U[0] R[1] = MUL CONST[0], R[0].xxxx R[2] = MAD CONST[1], R[0].yyyy, R[1] R[1] = MAD CONST[2], R[0].zzzz, R[2] R[0].xyz = ADD R[1].xyzx, CONST[3].xyzx R[0] = MOV T_TEX0.xyyy U[0] = TEXLD S[0],R[0] R[1].w = MOV U[0] R[0].w = MOV R[1].wwww oC = MOV R[0] END Note that T_TEX0 is copied to R[0], but the xyz components of R[0] are still expected to hold a calculated value. Fixes piglit tests draw-elements-vs-inputs, fp-kill, and glsl-fs-color-matrix. It also fixes Meego bugzilla #13005. NOTE: This is a candidate for the 7.9 and 7.10 branches.
* i965: Emit texel offsets in sampler messages.Kenneth Graunke2011-01-312-4/+43
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* Convert everything from the talloc API to the ralloc API.Kenneth Graunke2011-01-318-43/+42
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* r300/compiler: Standardize the number of bits used by swizzle fieldsTom Stellard2011-01-2910-46/+50
| | | | | | | | | | | | | | Swizzles are now defined everywhere as a field with 12 bits that contains 4 channels worth of meaningful information. Any channel that is unused is set to RC_SWIZZLE_UNUSED. This change is necessary because rgb instructions and alpha instructions were initializing channels that would never be used (channel 3 for rgb and channels 1-3 for alpha) with 0 (aka RC_SWIZZLE_X). This made it impossible to use generic helper functions for swizzles, because sometimes a channel value of 0 meant unused and other times it meant RC_SWIZZLE_X. All hacks that tried to guess how many channels were relevant have also been removed.
* r300/compiler: print stats based on the initial number of instructionsMarek Olšák2011-01-282-3/+10
| | | | | The same number of shaders is now printed regardless of optimizations being enabled or not, so that we can compare shader stats side by side easily.
* r600c: only colors can be flat shadedAndre Maasikas2011-01-242-36/+9
| | | | fixes stellarium text and menu display
* r300g: Increase fragment shader limits for r400 cardsTom Stellard2011-01-235-33/+205
| | | | | r400 fragment shaders now support up to 64 temporary registers, 512 ALU instructions, and 512 TEX instructions.
* i965: remove _NEW_ACCUMBrian Paul2011-01-231-1/+0
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* r300/compiler: remove any code related to relative addressing of temporariesMarek Olšák2011-01-239-120/+13
| | | | | The hw can't do it and the code was useless anyway (it's lowered in the GLSL compiler).
* glsl, i965: Remove unnecessary talloc includes.Kenneth Graunke2011-01-213-3/+0
| | | | These are already picked up by ir.h or glsl_types.h.
* r600c: get OQ results only for 4 DBs on r600 classAndre Maasikas2011-01-211-2/+6
| | | | | - since evergreen addition which increased this to 8 depth backends other bytes may contain garbage values
* intel: Fix typeos from 3d028024 and 790ff232Ian Romanick2011-01-202-15/+15
| | | | ...and remove egg from face.
* i915: Set correct values for range/precision of fragment shader typesIan Romanick2011-01-201-0/+14
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* i965: Set correct values for range/precision of fragment shader typesIan Romanick2011-01-201-0/+9
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* r600c: bump sq gpr resources if a shader needs more than defaultAndre Maasikas2011-01-202-0/+21
| | | | | | | | | | | | | ideally this should be set once in the beginning of CS but there's no way to change values there while in the middle of rendering. For now reemitting SQ setup seems to work probably due to r700WaitForIdleClean after each render currently does not to try to decrease values once increased fixes hangs in glsl-vs-vec4-indexing-temp-src-in-nested-loop-combined glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined for my rv740 maybe more for other chips
* r200: fix up some problems with TFP on r200Dave Airlie2011-01-201-5/+15
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* i965/fs: Take the shared mathbox into account in instruction scheduling.Eric Anholt2011-01-191-0/+15
| | | | | | I don't have evidence for this amounting to any improvement, but it does codify a bit more what we understand so far about the pipeline.
* i965/fs: Add a helper function for detecting math opcodes.Eric Anholt2011-01-192-8/+13
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* i965/fs: Assign URB/CURB register numbers after instruction scheduling.Eric Anholt2011-01-191-2/+3
| | | | | | | | | | | | This fixes a bunch of unnecessary barriers due to the scheduler not knowing what that arbitrary register description refers to when trying to reason about its dependencies. The result is rescheduling in the convolution kernel shader in Lightsmark, which results in avoiding register spilling and increasing the performance of the first scene from 6-7 fps midway through the panning to 11fps. The register spilling was a regression from Mesa 7.9 to Mesa 7.10.
* i965/fs: Add an instruction scheduler.Eric Anholt2011-01-194-0/+479
| | | | | | | Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also reschedules the giant multiply tree at the end of glsl-fs-convolution-1 so that we end up not spilling registers, producing the expected level of performance.
* i965/fs: Add a helper for detecting texturing opcodes.Eric Anholt2011-01-192-8/+12
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* radeon: avoid segfault on 3D textures.Dave Airlie2011-01-191-0/+3
| | | | This is a candidate for 7.9 and 7.10
* radeon: oops didn't need this logbase2 fnDave Airlie2011-01-191-15/+0
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* radeon: calculate complete texture state inside TFP functionDave Airlie2011-01-191-3/+25
| | | | | | (really not sure why I'm doing this). This is a candidate for 7.9 and 7.10 branches.
* dri/nouveau: allow multiple maps of surface buffersBen Skeggs2011-01-191-2/+4
| | | | | | | | | Can happen during swrast fallbacks if a buffer is somehow bound as a render target and a texture. Fixes gnome-shell on nv20, and gets it mostly working on nv10. Signed-off-by: Ben Skeggs <[email protected]>
* radeon/r200: fix fbo-clearmipmap + gen-teximageDave Airlie2011-01-193-6/+6
| | | | | | | | | | | sw clears were being used and not getting the correct offsets in the span code. also not emitting correct offsets for CB draws to texture levels. (I've no idea why I'm playing with r100). This is a candidate for 7.9 and 7.10
* i965: Fix a comment typo.Eric Anholt2011-01-181-1/+1
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* i965: Fix a bug in i965 compute-to-MRF.Eric Anholt2011-01-181-0/+1
| | | | | | Fixes piglit glsl-fs-texture2d-branching. I couldn't come up with a testcase that didn't involve dead code, but it's still worthwhile to fix I think.
* r600c: preserve correct buffer when using fboAndre Maasikas2011-01-181-1/+1
| | | | Hopefully better than previous - this passes more mipgen tests
* r600: set border color as RGBAAndre Maasikas2011-01-181-2/+2
| | | | border color is RGBA for samples - this passes texenv tests
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