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path: root/src/mesa/drivers/dri
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* mesa: Replace _mesa_program_index_to_target with _mesa_shader_stage_to_program.Paul Berry2014-01-211-1/+1
* i965: Ignore 'centroid' interpolation qualifier in case of persample shadingAnuj Phogat2014-01-211-1/+1
* i965: Use sample barycentric coordinates with per sample shadingAnuj Phogat2014-01-214-6/+30
* i965: Add an option to ignore sample qualifierAnuj Phogat2014-01-213-4/+4
* i965/fs: Optimize LRP with x == y into a MOV.Matt Turner2014-01-211-0/+10
* i965: Enable AOS optimizations for the geometry shader.Matt Turner2014-01-211-0/+1
* mesa: rename PreferDP4 to OptimizeForAOS.Matt Turner2014-01-213-3/+3
* i965/fs: Print the maximum register pressure.Matt Turner2014-01-211-1/+3
* i965/fs: Show register pressure in dump_instructions() output.Kenneth Graunke2014-01-213-1/+16
* i965: Compute the number of live registers at each IP.Kenneth Graunke2014-01-213-0/+22
* i965/fs: Call opt_peephole_sel later in the optimization loop.Matt Turner2014-01-211-1/+1
* i965/fs: Calculate interference better in register_coalesce.Matt Turner2014-01-211-7/+72
* i965/fs: Support coalescing registers of size > 1.Matt Turner2014-01-211-23/+59
* i965/fs: Assert that var < num_vars.Matt Turner2014-01-211-0/+2
* i965/fs: Add a comment explaining how register coalescing works.Matt Turner2014-01-211-0/+12
* i965/fs: Add and use MAX_SAMPLER_MESSAGE_SIZE definition.Matt Turner2014-01-213-5/+10
* i965/fs: Fix the example about overwriting uniforms in SIMD16.Matt Turner2014-01-211-5/+5
* i965: Print reg_offset for vgrf of size > 1 in dump_instruction().Matt Turner2014-01-212-4/+4
* i965: Modify some error messages to refer to "vec4" instead of "vs".Paul Berry2014-01-212-5/+5
* i965: Add GS support to INTEL_DEBUG=shader_time.Paul Berry2014-01-218-10/+37
* i965: Reserve space for "Vertex Count" in GS outputs.Kenneth Graunke2014-01-212-0/+13
* i965: Update blitter code for 48-bit addresses.Kenneth Graunke2014-01-201-16/+48
* i965: Update PIPE_CONTROL packet lengths for Broadwell.Kenneth Graunke2014-01-201-2/+20
* i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.Kenneth Graunke2014-01-203-23/+10
* i965: Create a helper function for emitting PIPE_CONTROL writes.Kenneth Graunke2014-01-204-93/+69
* i965: Use full-length PIPE_CONTROL packets for workaround writes.Kenneth Graunke2014-01-201-6/+9
* i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.Kenneth Graunke2014-01-201-2/+3
* i965: Create a helper function for emitting PIPE_CONTROL flushes.Kenneth Graunke2014-01-204-86/+66
* i965: Fix MI_STORE_REGISTER_MEM for Broadwell.Kenneth Graunke2014-01-201-10/+23
* i965: Introduce an OUT_RELOC64 macro.Kenneth Graunke2014-01-202-0/+34
* i965: Use the new drm_intel_bo offset64 field.Kenneth Graunke2014-01-2012-30/+30
* i965: Delete intel_batchbuffer_emit_reloc_fenced.Kenneth Graunke2014-01-202-30/+0
* i915: Silence warning: unused parameter warning in intel_bufferobj_bufferIan Romanick2014-01-203-13/+5
* i915: Ensure that intel_bufferobj_map_range meets alignment guaranteesIan Romanick2014-01-201-7/+21
* i965: Ensure that intel_bufferobj_map_range meets alignment guaranteesIan Romanick2014-01-201-7/+21
* i965: Enable ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-202-0/+17
* i965: Consider all viewports before enabling guardband clippingIan Romanick2014-01-201-5/+9
* i965: Consider only the scissor rectangle for viewport 0 for clearsIan Romanick2014-01-201-1/+1
* i965: Set all the supported scissor rectangles for GEN7Ian Romanick2014-01-201-27/+33
* i965: Set all the supported viewports for GEN7Ian Romanick2014-01-203-37/+48
* i965: Emit writes to viewport indexIan Romanick2014-01-202-3/+7
* i965: Set the maximum VPIndexIan Romanick2014-01-203-1/+5
* mesa: Convert gl_context::Viewport to gl_context::ViewportArrayCourtney Goeltzenleuchter2014-01-2011-38/+38
* mesa: Converty gl_viewport_attrib::X, ::Y, ::Width, and ::Height to floatCourtney Goeltzenleuchter2014-01-204-10/+10
* mesa: Update gl_scissor_attrib to support ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-209-34/+42
* i915,r200,radeon,vega: Change vendor from "VMware, Inc." to "Mesa Project".José Fonseca2014-01-202-2/+2
* i965/blorp: reduce the scope of the explicit compression controlTopi Pohjolainen2014-01-201-11/+20
* i965/blorp: remove dependency to compression control stateTopi Pohjolainen2014-01-201-4/+3
* i965: Only update renderbuffers on initial intelMakeCurrentKristian Høgsberg2014-01-191-1/+8
* i965: Double the push constant space multipliers on Broadwell too.Kenneth Graunke2014-01-181-2/+4