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* radeon: Provide a more detailled GL_RENDERER string.Nicolai Hähnle2009-06-013-5/+47
* r300: when using cs path emit scissor in the cmdbufferJerome Glisse2009-05-284-0/+43
* r300: rework texture offset emission.Jerome Glisse2009-05-281-7/+13
* radeon: emit scissor before emiting verticesJerome Glisse2009-05-271-3/+1
* radeon: emit scissor when using cs submission style.Jerome Glisse2009-05-271-0/+28
* radeon: on update drawable don't firevertices as it might be call from GetLockJerome Glisse2009-05-251-3/+1
* r200: emit scissor when dri2 is enabledJerome Glisse2009-05-251-0/+31
* r200: fix multitexturing in dri2 pathJerome Glisse2009-05-251-1/+1
* r200: emit cliprect with indexed primitiveJerome Glisse2009-05-251-1/+1
* radeon: realloc dma if needed after revalidateJerome Glisse2009-05-241-0/+6
* radeon: Remove drawable & readable from radeon_dri_mirrorNicolai Hähnle2009-05-2413-319/+310
* radeon: reading back to scratch reg through status map doesn't workJerome Glisse2009-05-221-2/+7
* radeon: maxbuffer size is in bytesJerome Glisse2009-05-211-2/+2
* r200: fix vbo array renderingJerome Glisse2009-05-202-4/+5
* radeon: Increase reference count of current renderbuffers.Michel Dänzer2009-05-204-10/+11
* Merge branch 'master' into radeon-rewriteMichel Dänzer2009-05-2018-75/+192
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| * Merge branch 'mesa_7_5_branch'Brian Paul2009-05-182-8/+21
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| | * r300: Make sure to drop current hardware state reference to texture objects.Michel Dänzer2009-05-142-8/+21
| * | intel: Don't complain on falling back from PBO fastpaths.Eric Anholt2009-05-151-3/+3
| * | i915: Fix 945 cube map layout for the small mipmaps along the bottom.Steinar H. Gunderson2009-05-151-2/+14
| * | i915: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers.Eric Anholt2009-05-151-1/+1
| * | i915: Only use the new 945 cube layout for compressed textures.Eric Anholt2009-05-151-1/+4
| * | i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-05-141-8/+10
| * | i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-05-144-13/+27
| * | intel: Use FRONT_AND_BACK for StencilOp as well.Eric Anholt2009-05-141-1/+2
| * | intel: Use GL_FRONT_AND_BACK for stencil clearing.Eric Anholt2009-05-141-1/+2
| * | i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-05-141-0/+10
| * | i965: send all warnings through _mesa_warning()Robert Ellison2009-05-141-1/+1
| * | Merge branch 'mesa_7_5_branch'Brian Paul2009-05-131-1/+2
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| | * intel: added null ptr checkBrian Paul2009-05-131-1/+2
| * | intel: enable GL_APPLE_vertex_array_objectBrian Paul2009-05-131-0/+2
| * | Merge branch 'mesa_7_5_branch'Brian Paul2009-05-133-29/+75
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| | * intel: create a private gl_array_object for intel_clear_tris(), fix bug 21638Brian Paul2009-05-133-29/+75
| | * Test either GL_FRONT_LEFT or GL_FRONT for front-buffer renderingIan Romanick2009-05-111-1/+2
| * | i965: enable additional code in emit_fb_write()Brian Paul2009-05-121-11/+10
| * | i965: increase BRW_EU_MAX_INSNBrian Paul2009-05-121-1/+1
| * | i965: commentBrian Paul2009-05-121-0/+4
| * | intel: Skip the DRI2 renderbuffer update when doing Viewport on an FBO.Eric Anholt2009-05-121-1/+1
| * | intel: Map write-only buffer objects through the GTT when possible.Eric Anholt2009-05-122-2/+15
| * | i915: Fix driver after HW glGenerateMipmap commit.Eric Anholt2009-05-121-0/+1
| * | i965: handle extended swizzle terms (0,1) in get_src_reg()Brian Paul2009-05-111-0/+8
* | | radeon: set max texture sizeJerome Glisse2009-05-203-0/+13
* | | r200: fix indexed draw color order and cs missmatchJerome Glisse2009-05-202-3/+6
* | | radeon: fix DRI1 cmd streamJerome Glisse2009-05-182-17/+18
* | | r300: cleanup vertex program related functionsMaciej Cencora2009-05-166-216/+164
* | | r300: minor code movementMaciej Cencora2009-05-161-21/+21
* | | r300: more cleanupMaciej Cencora2009-05-161-27/+13
* | | r300: move some code to common pathMaciej Cencora2009-05-162-21/+12
* | | r300: rename functionsMaciej Cencora2009-05-167-8/+8
* | | r300: move forward declarations to where they belongMaciej Cencora2009-05-162-4/+5