summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri
Commit message (Collapse)AuthorAgeFilesLines
* i915: Enable LOD preclamping on 8xx like on 915/965.Eric Anholt2011-01-052-0/+3
| | | | Fixes lodclamp-between and lodclamp-between-max.
* i915: Implement min/max lod clamping in hardware on 8xx.Eric Anholt2011-01-053-25/+32
| | | | | This avoids 8xx-specific texture relayout for min/max lod changes. One step closer to avoiding relayout for base/maxlevel changes!
* intel: Drop TEXTURE_RECTANGLE check in miptree layout setup.Eric Anholt2011-01-051-37/+24
| | | | | It's already handled by our non-mipmapped MinFilter, since TEXTURE_RECTANGLE is always NEAREST or LINEAR.
* intel: Clean up redundant setup of firstLevel.Eric Anholt2011-01-051-5/+4
| | | | | It's always BaseLevel (since TEXTURE_RECTANGLE's baselevel can't be changed from 0), except for 8xx minlod hilarity.
* intel: Drop a check for GL_TEXTURE_4D_SGIS.Eric Anholt2011-01-051-1/+0
| | | | | The SGIS_texture4D extension was thankfully never completed, so we couldn't implement it if we wanted to.
* i965: Simplify the renderbuffer setup code.Eric Anholt2011-01-051-102/+93
| | | | | | It was quite a mess by trying to do NULL renderbuffers and real renderbuffers in the same function. This clarifies the common case of real renderbuffers.
* i965: use BLT to clear buffer if possible on SandybridgeXiang, Haihao2011-01-051-6/+0
| | | | This fixes https://bugs.freedesktop.org/show_bug.cgi?id=32713
* i965: Add support for SRGB DXT1 formats.Eric Anholt2011-01-043-2/+10
| | | | | | | | | | This makes fbo-generatemipmap-formats GL_EXT_texture_sRGB-s3tc match fbo-generatemipmap-formats GL_EXT_texture_compression_s3tc and swrast in bad DXT1_RGBA alpha=0 handling, but it means we won't unpack and repack someone's textures into uncompressed SARGB8 format.
* intel: Merge our choosetexformat fallbacks into core.Eric Anholt2011-01-045-229/+60
| | | | | | We now share the type/format -> MESA_FORMAT_* mappings with software mesa, and the core supports most of the fallbacks hardware drivers will want.
* r300/compiler: disable the rename_regs pass for loopsMarek Olšák2011-01-041-0/+8
| | | | | | This workaround fixes rendering of kwin thumbnails. NOTE: This is a candidate for the 7.9 and 7.10 branches.
* r300/compiler: Fix black terrain in Civ4Tom Stellard2011-01-041-8/+1
| | | | | | | rc_inst_can_use_presub() wasn't checking for too many RGB sources in Alpha instructions or too many Alpha sources in RGB instructions. Note: This is a candidate for the 7.10 branch.
* intel: When validating an FBO's combined depth/stencil, use the given FBO.Eric Anholt2011-01-041-4/+4
| | | | | | | We were looking at the current draw buffer instead to see whether the depth/stencil combination matched. So you'd get told your framebuffer was complete, until you bound it and went to draw and we decided that it was incomplete.
* intel: Fix segfaults from trying to use _ColorDrawBuffers in FBO validation.Eric Anholt2011-01-041-4/+16
| | | | | | | | | | | | | | The _ColorDrawBuffers is a piece of computed state that gets for the current draw/read buffers at _mesa_update_state time. However, this function actually gets used for non-current draw/read buffers when checking if an FBO is complete from the driver's perspective. So, instead of trying to just look at the attachment points that are currently referenced by glDrawBuffers, look at all attachment points to see if they're driver-supported formats. This appears to actually be more in line with the intent of the spec, too. Fixes a segfault in my upcoming fbo-clear-formats piglit test, and hopefully bug #30278
* i965: Use last vertex convention for quad provoking vertex on sandybridgeZhenyu Wang2011-01-041-0/+7
| | | | | | | Until we know how hw converts quads to polygon in beginning of 3D pipeline, for now unconditionally use last vertex convention. Fix glean/clipFlat case.
* i965: Correct comment for gen6 fb write control message settingZhenyu Wang2011-01-041-1/+3
| | | | | Remove incorrect headless comment for gen6 fb write message. Note current SIMD16 mode has already done right for control message.
* i965: Fix provoking vertex select in clip state for sandybridgeZhenyu Wang2011-01-041-1/+4
| | | | | | | Triangle fan provoking vertex for first convention should be 'vertex 1' in sandybridge clip state. Partly fix glean/clipFlat case
* intel: Use tri clears when we don't know how to blit clear the format.Eric Anholt2011-01-033-7/+10
| | | | | Bug #32207. Fixes ARB_texture_rg/fbo-clear-formats (see my fbo-clear-formats piglit branch currently)
* intel: Handle forced swrast clears before other clear bits.Eric Anholt2011-01-031-22/+20
| | | | | Fixes a potential segfault on a non-native depthbuffer, and possible accidental swrast fallback on extra color buffers.
* radeon: fix build on non-KMS systems.Dave Airlie2011-01-031-0/+3
| | | | Reported on irc by adamk.
* i965: Do lowering of array indexing of a vector in the FS.Eric Anholt2010-12-281-0/+1
| | | | | Fixes a regression in ember since switching to the native FS backend, and the new piglit tests glsl-fs-vec4-indexing-{2,3} for catching this.
* i965: Fix regression in FS comparisons on original gen4 due to gen6 changes.Eric Anholt2010-12-282-4/+32
| | | | Fixes 26 piglit cases on my GM965.
* i965: Factor out the ir comparision to BRW_CONDITIONAL_* code.Eric Anholt2010-12-281-80/+34
|
* i965: Fix occlusion query on sandybridgeZhenyu Wang2010-12-281-0/+6
| | | | | | Clear target query buffer fixed occlusion query on sandybridge. https://bugs.freedesktop.org/show_bug.cgi?id=32167
* Revert "i965: upload multisample state for fragment program change"Zhenyu Wang2010-12-283-38/+25
| | | | | | | This reverts commit de6fd527a545f8344e074312544517d05573fb72. Revert this workaround as it seems the real trouble is caused by lineloop, which doesn't require GS convert on sandybridge actually.
* i965: Internally enable GL_NV_blend_square on ES2.Kenneth Graunke2010-12-271-0/+1
| | | | Hopefully should fix bug #32520.
* i965: don't spawn GS thread for LINELOOP on SandybridgeXiang, Haihao2010-12-271-1/+4
| | | | | LINELOOP is converted to LINESTRIP at the beginning of the 3D pipeline. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=32596
* i965: Flatten if-statements beyond depth 16 on pre-gen6.Kenneth Graunke2010-12-271-0/+10
| | | | | | | | | | Gen4 and Gen5 hardware can have a maximum supported nesting depth of 16. Previously, shaders with control flow nested 17 levels deep would cause a driver assertion or segmentation fault. Gen6 (Sandybridge) hardware no longer has this restriction. Fixes fd.o bug #31967.
* intel: Only do frame throttling at glFlush time when using frontbuffer.Eric Anholt2010-12-251-1/+2
| | | | | | | | | | | This is the hack for input interactivity of frontbuffer rendering (like we do for backbuffer at intelDRI2Flush()) by waiting for the n-2 frame to complete before starting a new one. However, for an application doing multiple contexts or regular rebinding of a single context, this would end up lockstepping the CPU to the GPU because every unbind was considered the end of a frame. Improves WOW performance on my Ironlake by 48.8% (+/- 2.3%, n=5)
* i965: use align1 access mode for instructions with execSize=1 in VSXiang, Haihao2010-12-241-0/+2
| | | | | All operands must be 16-bytes aligned in aligh16 mode. This fixes l_xxx.c in oglconform.
* i965: fix register region descriptionXiang, Haihao2010-12-241-1/+1
| | | | | This fixes brw_eu_emit.c:179: validate_reg: Assertion `width == 1' failed.
* intel: Remove unnecessary headers.Vinson Lee2010-12-232-2/+0
|
* i965: Remove unnecessary headers.Vinson Lee2010-12-231-2/+0
|
* i965: Keep around a copy of the VS constant surface dumping code.Eric Anholt2010-12-231-0/+9
| | | | | | Just like everywhere else, I never trust my constant uploads to correctly put constants in the right places, even though that's so rarely where the issue is.
* i965: Correct the dp_read message descriptor setup on g4x.Eric Anholt2010-12-233-1/+23
| | | | | | | It's mostly like gen4 message descriptor setup, except that the sizes of type/control changed to be like gen5. Fixes 21 piglit cases on gm45, including the regressions in bug #32311 from increased VS constant buffer usage.
* i965: upload multisample state for fragment program changeZhenyu Wang2010-12-233-25/+38
| | | | | This makes conformance tests stable on sandybridge D0 to track multisample state before SF/WM state.
* i965: Use MI_FLUSH_DW for blt ring flush on sandybridgeZhenyu Wang2010-12-232-2/+7
| | | | Old MI_FLUSH command is deprecated on sandybridge blt.
* i965: explicit tell header present for fb write on sandybridgeZhenyu Wang2010-12-224-8/+8
| | | | | | | | | Determine header present for fb write by msg length is not right for SIMD16 dispatch, and if there're more output attributes, header present is not easy to tell from msg length. This explicitly adds new param for fb write to say header present or not. Fixes many cases' hang and failure in GL conformance test.
* i965: Avoid using float type for raw moves, to work around SNB issue.Eric Anholt2010-12-212-4/+8
| | | | | | | | | | The SNB alt-mode math does the denorm and inf reduction even for a "raw MOV" like we do for g0 message header setup, where we are moving values that aren't actually floats. Just use UD type, where raw MOVs really are raw MOVs. Fixes glxgears since c52adfc2e1d130effea940e75690897eb5d3ceaa, but no piglit tests had regressed(!)
* intel: Check for unsupported texture when finishing using as a render targetChris Wilson2010-12-211-1/+2
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32541 Signed-off-by: Chris Wilson <[email protected]>
* nouveau: fix includes for latest libdrmBen Skeggs2010-12-211-1/+1
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* r600c : inline vertex format is not updated in an app, switch to use vfetch ↵richard2010-12-161-1/+1
| | | | constants. For the 7.9 and 7.10 branches as well.
* intel: Support glCopyTexImage() from XRGB8888 to ARGB8888.Eric Anholt2010-12-163-2/+94
| | | | | | The only mismatch between the two is that we have to clear the destination's alpha to 1.0. Fixes WOW performance on my Ironlake, from a few frames a second to almost playable.
* intel: Try to sanely check that formats match for CopyTexImage.Eric Anholt2010-12-161-40/+20
| | | | | | | | | Before, we were going off of a couple of known (hopeful) matches between internalFormats and the cpp of the read buffer. Instead, we can now just look at the gl_format of the two to see if they match. We should avoid bad blits that might have been possible before, but also allow different internalFormats to work without having to enumerate each one.
* intel: Drop commented intel_flush from copy_teximage.Eric Anholt2010-12-161-1/+0
| | | | | | The blit that follows appears in the command stream so it's serialized with previous rendering. Any queued vertices in the tnl layer were already flushed up in mesa/main/.
* intel: Update renderbuffers before looking up CopyTexImage's read buffer.Eric Anholt2010-12-161-3/+4
| | | | Not fixing a particular bug, just noticed by code inspection.
* i965: Set the alternative floating point mode on gen6 VS and WM.Eric Anholt2010-12-163-0/+8
| | | | | | | This matches how we did the math instructions pre-gen6, though it applies to non-math as well. Fixes vp1-LIT test 2 (degenerate case: 0 ^ 0 -> 1)
* i915: Fix INTEL_DEBUG=wm segmentation faultShuang He2010-12-161-5/+5
| | | | The program should be disassembled after it's uploaded
* i965: Add support for using the BLT ring on gen6.Eric Anholt2010-12-138-56/+72
|
* i965: Improve the hacks for ARB_fp scalar^scalar POW on gen6.Eric Anholt2010-12-131-36/+17
| | | | | | | | | | | | This is still awful, but my ability to care about reworking the old backend so we can just get a temporary value into a POW is awfully low since the new backend does this all sensibly. Fixes: fp1-LIT test 1 fp1-LIT test 3 (case x < 0) fp1-POW test (exponentiation) fp-lit-mask
* i965: Fix gl_FragCoord.z setup on gen6.Eric Anholt2010-12-131-2/+7
| | | | Fixes glsl-bug-22603.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 04:18:21 +0000