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path: root/src/mesa/drivers/dri
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* intel: fix EGLImage renderbuffer _BaseFormatFrank Henigman2015-03-032-3/+2
* i965: Fix assertion in brw_reg_type_lettersBen Widawsky2015-03-021-1/+1
* i965: Rename some PIPE_CONTROL flagsBen Widawsky2015-03-025-14/+14
* i965/fs: Don't use backend_visitor::instructions after creating the CFG.Matt Turner2015-03-021-10/+0
* i915: Remove hand-rolled memcpy implementation.Matt Turner2015-03-022-29/+1
* i965: Remove hand-rolled memcpy implementation.Matt Turner2015-03-022-28/+1
* i965: Consider scratch writes to have side effects.Matt Turner2015-03-021-0/+1
* radeon: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-10/+10
* r200: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-10/+10
* nouveau: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-4/+4
* i965: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-025-8/+8
* i915: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-1/+1
* i965: Remove the create_raw_surface vtbl hook.Francisco Jerez2015-03-025-47/+8
* i965: Add missing defines for render cache messages.Francisco Jerez2015-03-022-2/+8
* i965/skl: Lay out a 1D miptree horizontallyNeil Roberts2015-03-021-2/+60
* i965/skl: Lay out 3D textures the same as array texturesNeil Roberts2015-03-021-2/+8
* i965/skl: Fix the maximum thread count format for the PSNeil Roberts2015-03-021-1/+6
* i965/gs: Check newly-generated GS-out VUE map against correct stageChris Forbes2015-03-011-1/+1
* i965: add GLSL_TYPE_DOUBLE switch case to silence warningBrian Paul2015-02-281-0/+1
* i965/fs/nir: Mark fallthrough.Matt Turner2015-02-281-0/+1
* i965/fs/nir: Mark fallthrough.Matt Turner2015-02-281-0/+1
* i965: Avoid applying negate to wrong MAD source.Matt Turner2015-02-272-30/+26
* i965/vec4: Fix implementation of i2b.Matt Turner2015-02-271-1/+1
* i965/fs/nir: Use emit_math for nir_op_fpowIan Romanick2015-02-271-1/+1
* i965: Fix I/L/LA SNORM formats.Kenneth Graunke2015-02-271-1/+19
* i965/fs: Patch the instruction generating discards; don't use CMP.Z.Kenneth Graunke2015-02-271-2/+3
* i965/fs: Introduce brw_negate_cmod().Kenneth Graunke2015-02-272-0/+23
* swrast: replace INLINE with inlineBrian Paul2015-02-262-6/+6
* radeon: replace INLINE with inlineBrian Paul2015-02-265-8/+8
* r200: replace INLINE with inlineBrian Paul2015-02-263-4/+4
* i915: replace INLINE with inlineBrian Paul2015-02-2610-22/+22
* mesa: don't include math.h in compiler.hBrian Paul2015-02-261-0/+1
* mesa: include stdarg.h only where it's usedBrian Paul2015-02-261-0/+1
* i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRTAnuj Phogat2015-02-251-0/+3
* i965: Pass pointer to miptree as function parameter in intel_horizontal_textu...Anuj Phogat2015-02-251-6/+6
* i965: Allocate texture buffer in intelTexImageAnuj Phogat2015-02-251-2/+11
* i965: Make a function to check the conditions to use the blitterAnuj Phogat2015-02-251-11/+29
* i965: Move the comment to the right placeAnuj Phogat2015-02-251-1/+1
* i965: Fix condition to use Y tiling in blitter in intel_miptree_create()Anuj Phogat2015-02-251-3/+3
* i965: Don't force x-tiling for 16-bpp formats on Gen>7Neil Roberts2015-02-251-3/+3
* dri/common: Update comment about driQueryRendererIntegerCommonAndreas Boll2015-02-251-0/+1
* i965: Remove redundant discard jumps.Kenneth Graunke2015-02-242-0/+43
* i965/fs: Handle conditional discards.Kenneth Graunke2015-02-242-17/+26
* Revert "i965/fs: Remove force_writemask_all assertion for execsize < 8."Matt Turner2015-02-241-0/+1
* i965/fs: Emit MOV(1) instructions with force_writemask_all.Matt Turner2015-02-241-0/+1
* i965/fs: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.Matt Turner2015-02-242-0/+95
* i965/fs/nir: Optimize integer multiply by a 16-bit constant.Matt Turner2015-02-241-1/+23
* i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.Matt Turner2015-02-242-0/+90
* mesa: replace FABSF with fabsfBrian Paul2015-02-241-1/+2
* driconf: Update Catalan translationAlex Henrie2015-02-241-18/+34
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