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* mesa: Add scons files to distribution.Matt Turner2014-12-122-2/+2
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* mesa: Add clean-local rule to remove .lib links.Matt Turner2014-12-121-0/+6
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* xmlpool: Add $(MOS) and options.h to CLEANFILES.Matt Turner2014-12-121-0/+1
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* dri: Add uninstall hooks to handle megadriver hardlinks.Matt Turner2014-12-121-0/+5
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* swrast: Add headers to distribution.Matt Turner2014-12-121-1/+2
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* r200: Add headers to distribution.Matt Turner2014-12-122-2/+31
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* r200: Alphabetize source list.Matt Turner2014-12-121-10/+10
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* radeon: Add headers to distribution.Matt Turner2014-12-122-2/+31
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* radeon: Alphabetize source list.Matt Turner2014-12-121-9/+9
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* nouveau: Add headers to distribution.Matt Turner2014-12-122-1/+30
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* nouveau: Alphabetize source list.Matt Turner2014-12-121-10/+10
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* i965: Add headers to distribution.Matt Turner2014-12-121-0/+47
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* i965: Alphabetize source list.Matt Turner2014-12-121-35/+35
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* i915: Add headers to distribution.Matt Turner2014-12-121-1/+25
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* i915: Alphabetize source list.Matt Turner2014-12-121-23/+23
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* include: Add remaining headers to distribution.Matt Turner2014-12-121-1/+2
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* dri/common: Add files to distribution.Matt Turner2014-12-123-1/+7
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* dri/common: Drop unused mmio.h.Matt Turner2014-12-121-62/+0
| | | | Unused since commit 7550a24f.
* r200: Avoid out of bounds array access.Matt Turner2014-12-121-1/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/gen8+: Remove false perf debug message about MOCSBen Widawsky2014-12-111-3/+0
| | | | | | | | | | We support MOCS on both gen8 and gen9, so the message seems meaningless. Remove it to avoid confusion. Trivial. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Check correct number of blitter dwordsBen Widawsky2014-12-111-6/+6
| | | | | | | The odds of having this patch make a difference on Gen8+ are probably very low. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-but-not-tested-by: Jason Ekstrand <[email protected]>
* i965: Generate vs code using scalar backend for BDW+Kristian Høgsberg2014-12-106-15/+77
| | | | | | | | | | | | | | | | With everything in place, we can now use the scalar backend compiler for vertex shaders on BDW+. We make scalar vertex shaders the default on BDW+ but add a new vec4vs debug option to force the vec4 backend. No piglit regressions. Performance impact is minimal, I see a ~1.5 improvement on the T-Rex GLBenchmark case, but in general it's in the noise. Some of our internal synthetic, vs bounded benchmarks show great improvement, 20%-40% in some cases, but real-world cases are mostly unaffected. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Clean up fs_visitor::run and rename to run_fsKristian Høgsberg2014-12-102-19/+15
| | | | | | | | | Now that fs_visitor::run is back to being only fragment shader compilation, we can clean up a few stage == MESA_SHADER_FRAGMENT conditions and rename it to run_fs. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add fs_visitor::run_vs() to generate scalar vertex shader codeKristian Høgsberg2014-12-103-13/+436
| | | | | | | | | This patch uses the previous refactoring to add a new run_vs() method that generates vertex shader code using the scalar visitor and optimizer. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename brw_vec4_prog_data/key to brw_bue_prog_data/keyKristian Høgsberg2014-12-1013-42/+42
| | | | | | | | | | | These structs aren't vec4 specific, they are shared by shader stages operating on Vertex URB Entries (VUEs). VUEs are the data structures in the URB that hold vertex data between the pipeline geometry stages. Using vue in the name instead of vec4 makes a lot more sense, especially when we add scalar vertex shader support. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Prepare for using the ATTR register file in the fs backendKristian Høgsberg2014-12-104-6/+23
| | | | | | | | The scalar vertex shader will use the ATTR register file for vertex attributes. This patch adds support for the ATTR file to fs_visitor. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Consolidate code to get struct brw_sampler_prog_key_dataKristian Høgsberg2014-12-101-21/+16
| | | | | | | | This chunk of code is repeated in a few places, and we're going to add a MESA_SHADER_VERTEX case to it soon. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add new SIMD8 VS prog data flagKristian Høgsberg2014-12-106-7/+21
| | | | | | | | | | This flag signals that we have a SIMD8 VS shader so we can set up the corresponding state accordingly. This boils down to setting the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull constant buffers use dword pitch. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add SIMD8 URB write low-level IR instructionKristian Høgsberg2014-12-106-1/+51
| | | | | | | | | This is all we need from the generator for SIMD8 vertex shaders. This opcode is just the send instruction, all the hard work will happen in the visitor using LOAD_PAYLOAD. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove shader program argument and member from fs_generatorKristian Høgsberg2014-12-104-6/+3
| | | | | | | | Now that the caller passes in the shader debug name, we don't need this anymore. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Set shader name for generator from call siteKristian Høgsberg2014-12-104-24/+35
| | | | | | | | fs_generator no longer knows what stage it's generating code for, so we have to set the debug name of the shader from the call site. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generalize fs_generator furtherKristian Høgsberg2014-12-104-16/+12
| | | | | | | | This removes all stage specific data from the generator, and lets us create a generator for any stage. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't copy propagate constants from sources with saturateKristian Høgsberg2014-12-101-0/+2
| | | | | | | | We don't propagate the saturate bit and some instructions can't saturate at all. If the source has saturate set, just skip propagation. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Replace 'noann' debug flag with 'ann'.Matt Turner2014-12-103-3/+3
| | | | | | Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Disable unlit-centroid workaround on Gen < 6.Matt Turner2014-12-101-3/+0
| | | | | | | | | | | | | | | | | | | | | Back to the original commit (8313f444) adding the workaround, we were enabling it on gens <= 7, even though gens <= 5 can't do multisampling. I cannot find documentation that says that Sandybridge needs this workaround but in practice disabling it causes these piglit tests to fail: EXT_framebuffer_multisample/interpolation {2,4} centroid-deriv{,-disabled} On Ironlake: total instructions in shared programs: 4358478 -> 4349671 (-0.20%) instructions in affected programs: 117680 -> 108873 (-7.48%) A bunch of shaders in TF2, Portal 2, and L4D2 are cut by 25~30%. Cc: "10.4" <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* Remove useless checks for NULL before freeingMatt Turner2014-12-081-2/+1
| | | | | | | See commits 5067506e and b6109de3 for the Coccinelle script. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/skl: Add Skylake PCI IDsKristian Høgsberg2014-12-081-0/+29
| | | | Signed-off-by: Kristian Høgsberg <[email protected]>
* i965/skl: Emit depth stall workaround for gen9 as wellDamien Lespiau2014-12-081-1/+1
| | | | | | | | | | The docs say that we shouldn't need this workaround for gen8+, but just removing it, causes gpu hangs. We'll revisit this, but for now, just extend the workaround to gen9. Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/skl: Fix GS thread count locationBen Widawsky2014-12-081-11/+18
| | | | | | | | | | SKL moves the GS threadcount to dw8 from dw7, and no longer does the divide by 2 thing. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Kristian Høgsberg <[email protected]>
* i965: Fix union usage for G++ <= 4.6.Vinson Lee2014-12-081-1/+2
| | | | | | | | | | | | This patch fixes this build error with G++ <= 4.6. CXX test_vf_float_conversions.o test_vf_float_conversions.cpp: In function ‘unsigned int f2u(float)’: test_vf_float_conversions.cpp:63:20: error: expected primary-expression before ‘.’ token Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86939 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Remove default from brw_instruction_name switch to catch missing names.Matt Turner2014-12-081-12/+5
| | | | | | | The case-range extension is available in clang and gcc at least back to 3.4.0. Signed-off-by: Chris Forbes <[email protected]>
* i965: Add missing opcode names.Matt Turner2014-12-081-0/+9
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965: Add opcode names for set_omask and set_sample_id.Matt Turner2014-12-081-0/+4
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965/Gen6-7: Fix point sprites with PolygonMode(GL_POINT)Chris Forbes2014-12-071-0/+6
| | | | | | | | | | | | | | | | | This was an oversight in the original patch. When PolygonMode is used, then front faces, back faces, or both may be rendered as points and are affected by point sprite state. Note that SNB/IVB can't actually be fully conformant here, for a legacy context -- we don't have separate sets of pointsprite enables for front and back faces. Haswell ignores pointsprite state correctly in hardware for non-point rasterization, so can do this correctly, but it doesn't seem worth it. Signed-off-by: Chris Forbes <[email protected]> Cc: "10.4" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86764 Reviewed-by: Matt Turner <[email protected]>
* i965: Fix regs read for FS_OPCODE_INTERP_PER_SLOT_OFFSETChris Forbes2014-12-071-0/+2
| | | | | | | | | | Dead code elimination was eating the Y offset. Fixes the piglit test: spec/ARB_gpu_shader5/arb_gpu_shader5-interpolateAtOffset-nonconst Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add opcode names for FS interpolation opcodesChris Forbes2014-12-071-0/+9
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Perform CSE on MOV ..., VF instructions.Matt Turner2014-12-051-5/+11
| | | | | | | | | | | Safe from causing optimization loops, since we don't constant propagate VF arguments. (for this and the previous patch): total instructions in shared programs: 4289075 -> 4271932 (-0.40%) instructions in affected programs: 1616779 -> 1599636 (-1.06%) Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Try to emit LINE instructions on Gen <= 5.Matt Turner2014-12-052-0/+56
| | | | | | | | | | | | | The LINE instruction performs a multiply-add instruction (a * b + c) where b and c are scalar arguments. It reads b and c from offsets in src0 such that you can load them (it they're representable) as a vector-float immediate with a single instruction. Hurts some programs, but that'll all get better once we CSE the vector-float MOVs in the next patch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77544 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add support for generating the LINE instruction.Matt Turner2014-12-051-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Set the region of LINE's src0 to <0,1,0>.Matt Turner2014-12-051-1/+10
| | | | | | | | | | | | | The PRMs say that <src0> region must be a replicated scalar (with HorzStride = VertStride = 0). but apparently that doesn't actually apply to all generations. I did notice when implementing the optimization later in this series that G45 and ILK needed this regioning. Reviewed-by: Ian Romanick <[email protected]>
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