| Commit message (Collapse) | Author | Age | Files | Lines |
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Consistently just use C99's __func__ everywhere.
No functional changes.
Signed-off-by: Marius Predut <[email protected]>
Acked-by: Michel Dänzer <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
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We have two copies of it in the tree, I'm going to delete one.
Reviewed-by: Marek Olšák <[email protected]>
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Sed job:
grep -lr BEGIN_BATCH_NO_AUTOSTATE src/mesa/drivers/dri/ | while read f
do
cat $f | sed 's/BEGIN_BATCH_NO_AUTOSTATE/BEGIN_BATCH/g' > x
mv x $f
done
Signed-off-by: Ian Romanick <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Cc: Marek Olšák <[email protected]>
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radeon_context now contains a gl_context, rather than a pointer to one.
This will allow some minor core Mesa clean-up.
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This drops all the old drmSupports* checks since KMS does them all, and it
also drop R300_CLASS and R600_CLASS.
Signed-off-by: Dave Airlie <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
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It's past time, and it was going to get in the way of the renderbuffer
mapping refactor. We dropped all the other DRI1 drivers for this
release, and I can't imagine anybody supporting DRI1 radeon classic in
a new release of Mesa.
Diff produced by treating kernel_mm as true, deleting the DRI1 paths
that produce kernel_mm false, and deleting code.
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- since evergreen addition which increased this to 8 depth backends
other bytes may contain garbage values
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Based on initial patch from Stephan Schmid <[email protected]>.
Basic idea is to dump the zpass count at the start and end of the query
and subtract to get the total number of visible fragments. HW writes
alternating qwords for up to 4 DBs. On the first pass, we start at
buffer address + 0; on the second pass, we start at buffer address + 8
(bytes). The resulting buffer at the end of the query looks like:
qw[0]: db0 start
qw[1]: db0 end
...
qw[6]: db3 start
qw[7]: db3 end
The MSB of each qword is the valid bit and the lower 63 bits are
the zpass count for that DB.
OQ on RV740 is disabled at the moment as it only seems to report
results for half of its DBs. This needs further investigation.
Signed-off-by: Alex Deucher <[email protected]>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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