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* intel: Put the constant texcoords used in metaops into a vbo.Eric Anholt2009-05-085-40/+102
| | | | | | | Make this be its own function for setup/teardown of the binding of these texcoords. No performance difference in the engine demo (I just felt dirty not using a VBO for this), and I think it should be more resilient to interference from current GL state.
* intel: Unmap buffers if needed at DeleteBuffer time.Eric Anholt2009-05-061-1/+10
| | | | | | | This fixes a crash in glean's pbo test, which tripped over the assert when a context was destroyed while a buffer was still mapped (Mesa doesn't call UnmapBuffer in that case). Regression in c6bde8873fbda6d8467600b7491d8543c75b0509
* mesa: in glReadBufer() set _NEW_BUFFERS, not _NEW_PIXELBrian Paul2009-05-011-1/+1
| | | | | | | | | | | | | | | Since GL_READ_BUFFER is historically part of the gl_pixel_attrib group it made sense to signal changes with _NEW_PIXEL. But now with FBOs it's also part of the framebuffer state. Now _NEW_PIXEL strictly indicates pixels transfer state changes. This change avoids framebuffer state validation when any random bit of pixel-transfer state is set. DRI drivers updated too: don't check _NEW_COLOR when updating framebuffer state. I think that was just copied from the Xlib driver because we care about dither enable/disable state there.
* Test either GL_FRONT_LEFT or GL_FRONT for front-buffer renderingIan Romanick2009-05-011-1/+2
| | | | | | | | | | | For non-stereo visuals, which is all we support, we treat GL_FRONT_LEFT as GL_FRONT. However, they are technically different, and they have different enum values. Test for either one to determine if we're in front-buffer rendering mode. This fix was suggested by Pierre Willenbrock. Signed-off-by: Ian Romanick <[email protected]>
* i965: avoid segfault in intel_update_renderbuffers() if using DRI1Brian Paul2009-04-281-3/+4
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* intel: Fix more issues with the combined depth-stencil attachmentIan Romanick2009-04-241-6/+13
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* intel: Initialize region ptr to prevent assertion in intel_region_referenceIan Romanick2009-04-241-1/+1
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* intel / DRI2: When available, use DRI2GetBuffersWithFormatIan Romanick2009-04-242-16/+99
| | | | | | | | | | | This interface gives the driver two important features. First, it can allocate the (fake) front-buffer only when needed. Second, it can tell the buffer allocator the format of buffers being allocated. This enables support for back-buffer and depth-buffer with different bits per pixel. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* intel: Take advantage of GL_READ_ONLY_ARB to map to GEM bo_map write flag.Eric Anholt2009-04-231-3/+2
| | | | | This is a CPU win in general, but in particular reduces the pain of Mesa's calculation of min/max indices in DrawElements (wtf?).
* intel: fix max anisotropy supportedRoland Scheidegger2009-04-221-2/+0
| | | | | | i915 actually supports up to 4 (according to header file - not tested), i965 up to 16 (code already handled this but slightly broken), so don't use 2 for all chips, even though angular dependency is very high.
* intel: #include polygon.h to silence warningBrian Paul2009-04-181-0/+1
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* intel: Handle ARB_vertex_buffer_object state in intel_clear_tris().Michel Dänzer2009-04-181-0/+5
| | | | Fixes gearsvbo app by Michael Clark.
* intel: make sure polygon mode is set properly in intel_clear_tris()Brian Paul2009-04-171-0/+2
| | | | Fixes progs/glsl/skinning.c demo.
* intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.Eric Anholt2009-04-165-100/+200
| | | | | | Also enable them all regardless of screen bpp, as 32 bpp what I've been testing against, and haven't been able to detect any screen bpp-specific troubles with them.
* intel: fix small compressed texture uploadRoland Scheidegger2009-04-161-4/+5
| | | | | | | need to round up height for _mesa_copy_rect otherwise textures with height smaller than 4 won't get copied to the miptree at all Also fix up the confusing debug output (don't output unitialized values, and output if data is present and the compressed flag)
* i915: Add decode of dest buffer variables (destination format)Eric Anholt2009-04-151-0/+30
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* intel: Fix segfault when doing SW mipmap generation with a PBO texture upload.Eric Anholt2009-04-151-3/+10
| | | | | Triggered in test-fbo from clutter since 37fb2d9b23eab5dbbb43a212c3475cb8016837d8.
* DRI2: Don't fault on NULL DrawBufferIan Romanick2009-04-141-1/+1
| | | | | | | | | | It is possible for ctx->DrawBuffer to be NULL, so don't fault when that happens. This change is not being committed to master because it doesn't appear to be necessary there. Signed-off-by: Ian Romanick <[email protected]> Cherry picked from mesa_7_4_branch, commit 49e0c74ddd91900fc4effb6d305d56e0563b456d
* intel: added screen->dri2.loader null pointer check in intel_flush()Brian Paul2009-04-101-1/+2
| | | | Fixes segfaults when rendering to front buffer.
* intel / DRI2: Accept fake front-buffer from loaderIan Romanick2009-04-091-0/+5
| | | | | | | | | Handle the loader returning a fake front-buffer. Since the driver never specifically requests a fake front-buffer, the driver assumes that it will never receive both a fake and a real front-buffer. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* intel / DRI2: Track and flush front-buffer renderingIan Romanick2009-04-093-0/+46
| | | | | | | | | | | Track two flags: whether or not front-buffer rendering is currently enabled and whether or not front-buffer rendering has been enabled since the last glFlush. If the second flag is set, the front-buffer is flushed via a loader call back. If the first flag is cleared, the second flag is cleared at this time. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* intel: Avoid dri2 GetBuffers round-trips for internal Viewport calls.Eric Anholt2009-04-063-3/+10
| | | | | | This gets us the savings for driver-internal viewport calls that dd1c68f15123a889a3ce9d2afe724e272d163e32 was attempting, without relying on Xlib internals or clients handling X events.
* i965: Use GTT maps when available to upload vertex arrays and system VBOs.Eric Anholt2009-04-062-0/+7
| | | | | | | This speeds up OA on my GM45 by 21% (more than the original CPU cost of the upload path). We might still be able to squeeze a few more percent out by avoiding repeatedly mapping/unmapping buffers as we upload elements into them.
* intel: Clean up some a leftover from sedding of bufmgr context->screen move.Eric Anholt2009-04-061-3/+0
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* intel: #include texgetimage.hBrian Paul2009-04-031-0/+1
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* intel: Avoid mapping the texture image for CopyTex{,Sub}ImageAdam Jackson2009-03-301-11/+13
| | | | | | We don't upload the pixels with the CPU in that case, so the map will only serve as a way of triggering cache flushes over a bunch of data we don't touch.
* i965: srgb texture fixesRoland Scheidegger2009-03-281-5/+14
| | | | | | | | i965 can either do SRGBA8_REV format or SARGB8 format, but not SRGBA8. Could add SRGBA8_REV support to mesa, but simply use SARGB8 for now. While here, also add true srgb luminance / luminance_alpha support - unfortunately the published docs fail to mention which asics support this, tested on g43 so assume this works on any g4x.
* i965: add support for signed rgba texture formatRoland Scheidegger2009-03-282-0/+5
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* fix various small intel blitter issuesRoland Scheidegger2009-03-281-11/+12
| | | | | | use color format constants instead of magic numbers remove handling of cpp 0 or 3 (neither is possible) in various places don't misconfigure 8 bit surface blits as rgb565
* i965: Fix trailing "d" in debug output for 3DSTATE_VERTEX_ELEMENTS.Eric Anholt2009-03-231-1/+1
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* Fix DRI2 accelerated EXT_texture_from_pixmap with GL_RGB format.Eric Anholt2009-03-203-2/+19
| | | | | | | | | | | | | | This requires upgrading the interface so that the argument to glXBindTexImageEXT isn't just dropped on the floor. Note that this only fixes the accelerated path on Intel, as Mesa's texture format support is missing x8r8g8b8 support (right now, GL_RGB textures get uploaded as a8r8gb8, but in this case we're not doing the upload so we can't really work around it that way). Fixes bugs with compositors trying to use shaders that use alpha channels, on windows without a valid alpha channel. Bug #19910 and likely others as well. Reviewed-by: Ian Romanick <[email protected]>
* i965: add support for ATI_envmap_bumpmapRoland Scheidegger2009-03-122-0/+6
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* intel: include main/viewport.hBrian Paul2009-03-111-0/+1
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* mesa: remove last of _mesa_unreference_framebuffer() callsBrian Paul2009-03-071-1/+1
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* intel: Fix bpp setting of blits to 8bpp targets.Eric Anholt2009-03-051-0/+2
| | | | | This was causing hangs in cairogears, as we would blit to the 8bpp target (A8 texture) as 16bpp, and stomp over state objects.
* i965: fix 3DPRIMITIVE batch decode of the vertex count field.Eric Anholt2009-03-051-1/+1
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* intel: Add always_flush_batch driconf option for making small batchbuffers.Eric Anholt2009-03-053-1/+8
| | | | | This can improve debugging with INTEL_DEBUG=batch,sync by giving smaller batchbuffers.
* intel: Add always_flush_cache driconf option for debugging cache flush failure.Eric Anholt2009-03-054-2/+9
| | | | | I keep wanting to hack this knob in as a one-time thing, so it seemed useful to have all the time.
* i965: Add a note about why the _NEW_STENCIL is required in draw_buffers.Eric Anholt2009-03-051-0/+5
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* intel: Remove a gratuitous MI_FLUSH after clearing with a blit.Eric Anholt2009-03-051-1/+0
| | | | | The 3D destination shares the same cache so we don't have any trouble with the later commands needing the writes flushed inside of the same batchbuffer.
* i965: Remove dead flushing code.Eric Anholt2009-03-051-1/+0
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* i965: fix screen depth test in intel_validate_framebuffer)_Brian Paul2009-03-051-1/+2
| | | | front_region may be null.
* i965: add software fallback for conformant 3D textures and GL_CLAMPRobert Ellison2009-03-042-3/+14
| | | | | | | | | | | | | | | | | The i965 hardware cannot do GL_CLAMP behavior on textures; an earlier commit forced a software fallback if strict conformance was required (i.e. the INTEL_STRICT_CONFORMANCE environment variable was set) and 2D textures were used, but it was somewhat flawed - it could trigger the software fallback even if 2D textures weren't enabled, as long as one texture unit was enabled. This fixes that, and adds software fallback for GL_CLAMP behavior with 1D and 3D textures. It also adds support for a particular setting of the INTEL_STRICT_CONFORMANCE environment variable, which forces software fallbacks to be taken *all* the time. This is helpful with debugging. The value is: export INTEL_STRICT_CONFORMANCE=2
* mesa: use Stencil._Enabled field instead of Stencil.EnabledBrian Paul2009-03-024-5/+5
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* mesa: remove unused AUX buffersBrian Paul2009-03-021-4/+1
| | | | | | Remove all references to aux buffers 1..3. Keep AUX0 around for now just in case, but it'll probably go too someday. I don't know of any OpenGL drivers since the IRIX days that support aux color buffers.
* intel: remove some unneeded buffer unmap callsBrian Paul2009-02-271-14/+2
| | | | Core mesa now unmaps the buffers if needed in these cases.
* i915: Add support for a new G33-like chipset.Shaohua Li2009-02-272-2/+13
| | | | | Signed-off-by: Shaohua Li <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* intel: no-op the intel_finish_render_texture() functionBrian Paul2009-02-261-13/+10
| | | | It doesn't have to do anything. See comments for more details.
* intel: check texture formats in intel_validate_framebuffer()Brian Paul2009-02-261-0/+29
| | | | | | | | | We can't render into any texture format; only certain formats. Check that render-to-texture's format is renderable in the intel_validate_framebuffer() There seems to be a bug somewhere that causes rendering to rgb565 textures to be corrupted so disallow that for now. This will be revisted.
* intel: updated comment, some debug code (disabled)Brian Paul2009-02-261-3/+12
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