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* intel: Define span functions for S8 renderbuffersChad Versace2011-06-081-0/+64
| | | | | | | | | Since the stencil buffer is interleaved, the generic Mesa renderbuffer accessors do not suffice. Custom span functions are necessary. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Update intel-decode.c from intel-gpu-tools.Eric Anholt2011-06-072-88/+785
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* intel: Implement glFinish() correctly by waiting on all previous rendering.Eric Anholt2011-06-073-16/+13
| | | | | Before, we were waiting for (most of) the current framebuffer to be done, which is not quite the same thing.
* intel: Remove unused NO_TILE macroIan Romanick2011-05-311-3/+0
| | | | Reviewed-by: Eric Anholt <[email protected]>
* intel: Drop doubly irrelevant code in intelReadBuffers.Eric Anholt2011-05-261-12/+0
| | | | | | | | First, FBO read/draw == NULL validation happens in mesa core not intelReadBuffers -> intel_draw_buffers. Second, that condition is no longer tested for in our driver since ARB_ES2_compatibility was added. Reviewed-by: Brian Paul <[email protected]>
* intel: Change FBO validation criteria to accomodate hiz and seprate stencilChad Versace2011-05-251-15/+27
| | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Fix intel_draw_buffer() to accomodate hiz and separate stencilChad Versace2011-05-251-5/+11
| | | | | | | | The logic of intel_draw_buffers() expected that stencil buffers were always combined depth/stencil. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add hiz_region to intel_mipmap_treeChad Versace2011-05-253-0/+36
| | | | | | | | | | When a texture is attached to multiple FBO's, a separate renderbuffer wrapper is created for each attachment. This necessitates storing the hiz region for these renderbuffers in the texture itself instead of the renderbuffer wrapper. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Refactor the wrapping of textures with renderbuffersChad Versace2011-05-251-7/+8
| | | | | | | | | | | | | Before this commit, the renderbuffer's region was updated in intel_renderbuffer_texture(). This commit moves the update into intel_update_wrapper(), which is a more logical location for updates. This is in preparation for the next commit, which allocates and updates the texture's hiz region in intel_update_wrapper(). Having the two region updates located in the same function makes good form. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add hiz_region to intel_renderbufferChad Versace2011-05-252-0/+46
| | | | | | | | | | | | | | | | | | | | | | A hiz surface must be supplied to the hardware when rendering to a depth buffer with hiz. There are three potential places to store that surface: 1. Allocate a larger intel_region for the depthbuffer, and let the region's tail be the hiz surface. 2. Allocate a separate intel_region for hiz, and store it as brw_context state. 3. Allocate a separate intel_region for hiz, and store it in intel_renderbuffer. We choose method 3. Method 1 has not been chosen due to future complications it might cause when requesting a DRI drawable's depth buffer attachment from X. Method 2 has not been chosen because storing the hiz region apart from the depth region makes lazy hiz/depth resolves difficult to implement. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add is_hiz_depth_format() to intel_contex.vtblChad Versace2011-05-251-0/+4
| | | | | | | | | Given a format, is_hiz_depth_format() indicates if HiZ can be enabled on a depthbuffer of that format. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Allocate region for separate stencil bufferChad Versace2011-05-251-3/+30
| | | | | | | | | ... in intel_alloc_renderbuffer_storage(). The stencil buffer has quirky pitch requirements, so its region allocation is a special case. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Change supported texture formats for separate stencilChad Versace2011-05-252-1/+7
| | | | | | | | | | | When hardware supports separate stencil, enable support for separate depth/stencil texture formats in the table intel_context.ctx.TextureFormatsSupported. If the hardware must use separate stencil, then disable support for combined depth/stencil formats. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add flags to intel_context for hiz and separate stencilChad Versace2011-05-252-0/+58
| | | | | | | | | | | | | | | | | | | Add the following flags: intel_context.has_separate_stencil intel_context.must_use_separate_stencil intel_context.has_hiz The flags are currently set to false, and will be enabled for a given chipset once the feature is completely implemented. Since it may be some time before these features are completed, their values can be overridden with environment variables INTEL_HIZ and INTEL_SEPARATE_STENCIL. Valid values for these environment variables are "0" and "1". Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Add support for rendering to depthbuffer mipmap levels > 0.Eric Anholt2011-05-182-0/+39
| | | | | | Fixes GL_ARB_depth_texture/fbo-clear-formats GL_EXT_packed_depth_stencil/fbo-clear-formats
* i965: Rename IS_GT1 and IS_GT2 to IS_SNB_GT1 and IS_SNB_GT2.Kenneth Graunke2011-05-181-3/+3
| | | | | | This should help distinguish Sandybridge GT1/GT2 from Ivybridge GT1/GT2. Signed-off-by: Kenneth Graunke <[email protected]>
* intel: Recognize new Ivybridge PCI IDs.Kenneth Graunke2011-05-172-2/+22
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Initial IS_GEN7 plumbing.Kenneth Graunke2011-05-173-3/+17
| | | | | | | | | Currently, IS_GEN7, IS_IVYBRIDGE, IS_IVB_GT1, and IS_IVB_GT2 all return false. This allows me to write the code for them before actually adding the PCI IDs and thus enabling the hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* egl: Add a cursor use bit to MESA_drm_imageKristian Høgsberg2011-05-061-1/+9
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* Revert "intel: use throttle ioctl for throttling"Eric Anholt2011-04-273-3/+13
| | | | | | | | | | | | | This reverts commit 50ade6ea697953bb17e3ca7210515fbd0411cd1e. Fixes jerky rendering again on apps that don't block on the GPU per frame and are GPU bound (e.g. 3DMMES on Ironlake). The whole point of this complicated throttle scheme is to wait on frame n-1 to have started rendering before starting frame n's rendering. Otherwise, the GPU-bound app will race ahead and call the GL to draw many nearly-identical frames, then >0ms later get stuck waiting for them (all dispatched at about the same time) to retire, then render a new batch of nearly-identical frames.
* Squashed commit of the following:Brian Paul2011-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 864fe253b04105b7469e5f7b064dc37637b944f8 Author: Brian Paul <[email protected]> Date: Thu Apr 21 20:13:07 2011 -0600 mesa: s/exec/disp/ in _mesa_init_histogram_dispatch() This function isn't normally compiled (FEATURE_histogram). commit f4bf45e2b94b582cacd19cdca873c5be627e4250 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:58 2011 -0600 mesa: hook up GL_ARB_robustness dispatch functions ...and advertise the extension. Signed-off-by: Brian Paul <[email protected]> commit 2b89e38e5f572dc40cebc06381ae7c5d04386998 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:58 2011 -0600 mesa: regenerated API files for GL_ARB_robustness Signed-off-by: Brian Paul <[email protected]> commit 5d5ebfb7135cec9d833adef86cbf4d0f3d9beca8 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 glapi: add ARB_robustness xml Signed-off-by: Brian Paul <[email protected]> commit 0159d1d6d99f4bbc18381dc2081c20d3aff17ac9 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 mesa: implement GL_ARB_robustness functions Signed-off-by: Brian Paul <[email protected]> commit 938fd71f4c4742f274922d53492a7290ab8d9c9b Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 mesa: add context fields for GL_ARB_robustness Signed-off-by: Brian Paul <[email protected]> commit 72075137bc79e65be03dac7e97b6dba93c3a86a4 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 mesa: standardize more bounds-checking error messages Signed-off-by: Brian Paul <[email protected]> commit 32a3fc23746db49da903fbc08afa0135af3007d2 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 mesa: standardize some bounds-checking error messages Signed-off-by: Brian Paul <[email protected]> commit cecbf1f4d164207de373dec0cadee2e84e1f9656 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 mesa: add more bounds-checking support for client memory buffers Signed-off-by: Brian Paul <[email protected]> commit edc895b52383d5bd274422db56adead1d81daf5f Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 mesa: add bounds-checking support for client memory buffers Signed-off-by: Brian Paul <[email protected]> commit 3a96ef28a538f158a219b406cd090dee70470c85 Author: nobled <[email protected]> Date: Thu Apr 21 07:53:57 2011 -0600 mesa: use is_bufferobj() helper function Signed-off-by: Brian Paul <[email protected]>
* intel: Use tiling for dri2AllocateBuffer implementationKristian Høgsberg2011-04-261-1/+10
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* intel: Set gen in intelInitScreen, just copy value in intelInitContextKristian Høgsberg2011-04-263-5/+14
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* intel: Use X tiling for DRM EGL ImagesKristian Høgsberg2011-04-261-1/+1
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* intel: Add support for ARB_sampler_objects.Eric Anholt2011-04-232-3/+9
| | | | | | | | | | | | This extension support consists of replacing "gl_texture_obj->Sampler." with "_mesa_get_samplerobj(ctx, unit)->". One instance of referencing the texture's base sampler remains in the initial miptree allocation, where I'm not sure we have a clear association with any texture unit. Tested with piglit ARB_sampler_objects/sampler-objects. Reviewed-by: Brian Paul <[email protected]>
* i965: Add support for NV_conditional_render.Eric Anholt2011-04-234-0/+13
| | | | | | | | Since we lack hardware support for it, this is a simple matter of checking _mesa_check_conditional_render at the entrypoints, and suppressing it for the metaops where it doesn't apply. Reviewed-by: Brian Paul <[email protected]>
* i965: Add support for ARB_texture_compression_rgtc.Eric Anholt2011-04-232-0/+7
| | | | | | | | Tested with rgtc-teximage-0[12]. EXT_texture_compression_rgtc/fbo-generatemipmap-formats fails in NPOT just like S3TC does. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for ARB_color_buffer_float.Eric Anholt2011-04-201-0/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for ARB_texture_float.Eric Anholt2011-04-205-1/+31
| | | | | | | | | | | | For 1 and 2-channel formats the hardware only supports rendering to R and RG. To do I and L render targets we just call them R and everything works out. For A, we would need to rewrite the CC to do the alpha channel's blending on color instead, and send the fragment alpha down the red channel. For LA, there doesn't seem to be any hope, because we can't do independent color/alpha blending while treating the LA surface as RG. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for blit copies of >32bpp formats.Eric Anholt2011-04-201-0/+11
| | | | | | | | | The blitter only does up 32bpp at a time, so we handle it by mangling coordinates and calling the surface 32bpp. Fixes ARB_texture_rg/fbo-generatemipmap-formats-float with ARB_texture_float. Reviewed-by: Brian Paul <[email protected]>
* intel: Add I8 and L8 to intel_mesa_format_to_rb_datatype().Eric Anholt2011-04-181-0/+2
| | | | | | Fixes warnings in fbo-storage-formats. Reviewed-by: Brian Paul <[email protected]>
* intel: Use mesa core's R8, RG88, R16, RG1616 RB accessors.Eric Anholt2011-04-181-25/+4
| | | | | | | Fixes: ARB_texture_rg/fbo-alphatest-formats Reviewed-by: Brian Paul <[email protected]>
* intel: Use Mesa core's renderbuffer accessors for depth.Eric Anholt2011-04-181-33/+15
| | | | | | | | | | | Since we're using GTT mappings now (no manual detiling), there's really nothing special to accessing these buffers, other than needing the new RowStride field of gl_renderbuffer to accomodate padding. Reduces the driver size by 2.7kb, and improves glean depthStencil performance 3-10x (!) Reviewed-by: Brian Paul <[email protected]>
* intel: Use _mesa_base_tex_format for FBO texture attachments.Eric Anholt2011-04-181-1/+1
| | | | | | | | | | | | The _mesa_base_fbo_format variant doesn't handle some texture internalformats, such as "3". Fixes: fbo-blending-formats. fbo-alphatest-formats EXT_texture_sRGB/fbo-alphatest-formats Reviewed-by: Brian Paul <[email protected]>
* Merge branch 'arb_sampler_objects'Brian Paul2011-04-112-3/+3
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| * mesa: move sampler state into new gl_sampler_object typeBrian Paul2011-04-102-3/+3
| | | | | | | | | | | | gl_texture_object contains an instance of this type for the regular texture object sampling state. glGenSamplers() generates new instances of gl_sampler_object which can override that state with glBindSampler().
* | intel: Fix ROUND_DOWN_TO macroIan Romanick2011-04-111-3/+27
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the macro would (ALIGN(value - alignment - 1, alignment)). At the very least, this was missing parenthesis around "alignment - 1". As a result, if value was already aligned, it would be reduced by alignment. Condisder: x = ROUND_DOWN_TO(256, 128); This becomes: x = ALIGN(256 - 128 - 1, 128); Or: x = ALIGN(127, 128); Which becomes: x = 128; This macro is currently only used in brw_state_batch (brw_state_batch.c). It looks like the original version of this macro would just use too much space in the batch buffer. It's possible, but not at all clear to me from the code, that the original behavior is actually desired. In any case, this patch does not cause any piglit regressions on my Ironlake system. I also think that ALIGN_FLOOR would be a better name for this macro, but ROUND_DOWN_TO matches rounddown in the Linux kernel. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Keith Whitwell <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri: Remove driver date from renderer stringIan Romanick2011-04-051-5/+1
| | | | | | Reviewed-by: Corbin Simpson <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Sedat Dilek <[email protected]>
* i965: Add the missing supportable EXT_texture_snorm formatsIan Romanick2011-04-041-0/+5
| | | | | | | | | | | | This class of hardware can natively sample all of the snorm surface formats that DX10 requires, but it can't do some of the legacy GL formats. In particular, all of the alpha, luminance, and intensity formats are unsupported. This partially fixes the breakage in glean's pixelFormats test since GL_EXT_texture_snorm support was added to Mesa. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Fix regression in clear_with_blit from 7bae1c3dChris Wilson2011-03-311-11/+12
| | | | | | | | | | Oops, the mask was being used in the loop to determine whether to use include the stencil || depth values. This began to fail when mask was cleared at the beginning of the loop. So reorder the tests and do the work up-front along with determining the depth_stencil value to use. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35822 Signed-off-by: Chris Wilson <[email protected]>
* intel: Remove the unrelaxed relocation assertionChris Wilson2011-03-301-4/+0
| | | | | | | Now that we purposefully generate delta that point outside of the target buffer, the assertion has outlived its usefulness. Signed-off-by: Chris Wilson <[email protected]>
* intel: Add some defense against buffer allocation failure for subimage blitsChris Wilson2011-03-301-1/+9
| | | | | | | Once more! This time without the unwarranted conversion from drm_intel_bo_alloc_tiled. Signed-off-by: [a very embarrassed] Chris Wilson <[email protected]>
* Revert "intel: Add some defense against buffer allocation failure for ↵Chris Wilson2011-03-301-11/+11
| | | | | | | | | | | | | | subimage blits" This reverts commit de7678ef521f4fb34459e407a66ab8bf8be733e1. The conversion from using drm_intel_bo_alloc_tiled to a plain drm_intel_bo_alloc forgot that the tiled variant adjusts the allocation height even for TILING_NONE. Reported-by: Dave Airlie <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35786 Signed-off-by: Chris Wilson <[email protected]>
* intel: Add IS_GT2 macro for recognizing Sandybridge GT2 systems.Kenneth Graunke2011-03-291-8/+7
| | | | Also, refactor IS_GEN6 to use the IS_GT1 and IS_GT2 macros.
* intel: Protect intel_clear_with_blit from failed buffer allocationsChris Wilson2011-03-291-10/+11
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34419 Signed-off-by: Chris Wilson <[email protected]>
* intel: Don't leak the tex object miptree when replacing itIan Romanick2011-03-281-1/+3
| | | | | | | | | | | Eventually the miptree refcounting interface should be cleaned up. The assymmetry dramatically increases the probability of bugs like this. It should be made to like like libdrm refcounting or the refcounting style used in other parts of Mesa. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=33046 Reviewed-by: Eric Anholt <[email protected]>
* mesa: replace NEED_SECONDARY_COLOR(), RGBA_LOGICOP_ENABLED() with inlinesBrian Paul2011-03-111-1/+1
| | | | and rename them.
* intel: Don't complain when getparam fails due to a missing param.Eric Anholt2011-03-091-1/+3
| | | | | This is an expected behavior when we're testing for the presence of new kernel features.
* intel: check for miptree allocation failureChris Wilson2011-03-071-0/+2
| | | | Signed-off-by: Chris Wilson <[email protected]>
* intel: Add some defense against buffer allocation failure for subimage blitsChris Wilson2011-03-071-11/+11
| | | | Signed-off-by: Chris Wilson <[email protected]>
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