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path: root/src/mesa/drivers/dri/intel
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* intel: Fix unused variable warning.Eric Anholt2011-08-021-1/+0
* i965: Remove the now unused intel_renderbuffer::draw_offset field.Kenneth Graunke2011-07-282-2/+0
* i965: Check actual tile offsets in Gen4 miptree workaround.Kenneth Graunke2011-07-281-2/+17
* i965: Use 3D clears on gen6+ to avoid inter-ring synchronization.Eric Anholt2011-07-251-2/+2
* i965: Emit texture cache flushes on gen6 along with render cache flushes.Eric Anholt2011-07-251-0/+1
* Merge branch 'remove-copyteximage-hook'Brian Paul2011-07-211-97/+0
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| * intel: remove intelCopyTexImage1D/2D()Brian Paul2011-07-191-97/+0
* | i965: Enable the PIPE_CONTROL workaround workaround out of paranoia.Eric Anholt2011-07-202-3/+29
* | i965: Avoid kernel BUG_ON if we happen to wait on the pipe_control w/a BO.Eric Anholt2011-07-201-1/+1
* | intel: Use the GLSL-based meta clear when available.Eric Anholt2011-07-201-1/+4
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* intel: Fix stencil buffer to be W tiledChad Versace2011-07-195-31/+93
* i965: Rename 3DSTATE_DRAWRECT_INFO_I965 to 3DSTATE_DRAWING_RECTANGLE.Kenneth Graunke2011-07-181-1/+0
* i915: Simplify intel_wpos_* with a helper function.Eric Anholt2011-07-181-1/+0
* intel: Move intel_draw_buffers() code into each driver.Eric Anholt2011-07-183-200/+9
* intel: Clarify the depthRb == stencilRb logic.Eric Anholt2011-07-181-16/+15
* intel: Use the post-execution batchbuffer contents for dumping.Eric Anholt2011-07-181-1/+3
* i915: Fix map/unmap mismatches from leaving INTEL_FALLBACK during TNL.Eric Anholt2011-07-121-0/+1
* intel: Use _mesa_tex_target_to_face() helper function instead of our own.Eric Anholt2011-07-121-22/+3
* intel: Make our context structure be a ralloc context.Eric Anholt2011-07-111-2/+2
* intel: Recognize all depth formats in get_teximage_readbuffer.Kenneth Graunke2011-07-091-8/+4
* intel: add null src pointer check in intel_region_reference()Brian Paul2011-07-071-1/+2
* intel: Fix use of freed buffer if glBitmap is called after a swap.Eric Anholt2011-07-071-3/+4
* intel: Remove dead comment about software clears -- it's handled just above.Eric Anholt2011-07-071-1/+0
* i915: Fix leak of ViewportMatrix data on context destroy.John2011-07-071-0/+2
* intel: Remove gratuitous context checks in intel_delete_renderbuffer().Eric Anholt2011-07-071-14/+5
* intel: Remove now trivial intel_renderbuffer_set_{hiz_,}region().Eric Anholt2011-07-073-57/+19
* intel: Rely on intel_region_reference()'s support of *dst != NULL.Eric Anholt2011-07-072-14/+0
* intel: Allow intel_region_reference() with *dst != NULL.Eric Anholt2011-07-071-4/+6
* intel: Mark MESA_FORMAT_X8_Z24 as always supported.Eric Anholt2011-07-071-1/+1
* intel: Fix workaround for _mesa_update_framebufferChad Versace2011-06-241-3/+5
* intel: Change framebuffer validation criteriaChad Versace2011-06-241-10/+3
* intel: In intel_update_wrapper, support s8z24 textures when using separate st...Chad Versace2011-06-241-6/+35
* intel: Factor region updates out of intel_update_wrapperChad Versace2011-06-241-0/+18
* intel: During glTexImage, allocate renderbuffers for faking s8z24 texturesChad Versace2011-06-241-0/+62
* intel: Declare some functions in intel_fbo.c as non-staticChad Versace2011-06-242-2/+14
* intel: Change signature of intel_create_wrapped_renderbufferChad Versace2011-06-242-22/+12
* intel: Perform gather on s8z24 texture images during glGetTexImageChad Versace2011-06-241-0/+8
* intel: Define functions intel_texture_s8z24_scatter/gatherChad Versace2011-06-241-0/+70
* intel: Add fields to intel_texture for faking s8z24 with separate stencilChad Versace2011-06-243-12/+40
* i965: Don't bother telling swrast_setup about state updates until fallback.Eric Anholt2011-06-241-1/+0
* i965: Don't bother telling tnl about state updates unless we fall back.Eric Anholt2011-06-241-2/+0
* intel: Implement DRIimageExtension::dupImageBenjamin Franzke2011-06-231-1/+26
* intel: Allocate s8_z24 non-texture renderbuffers when using separate stencilChad Versace2011-06-211-3/+81
* intel: Unobfuscate intel_alloc_renderbuffer_storageChad Versace2011-06-211-17/+17
* intel: Add fields to intel_renderbuffer for unwrapping packed depth/stencil b...Chad Versace2011-06-214-44/+118
* intel: Unconditionally enable support for S8_Z24 texture formatChad Versace2011-06-211-1/+1
* i965/gen6: Apply documented workaround for nonpipelined state packets.Eric Anholt2011-06-202-1/+22
* i965/gen6: Limit the workaround flush to once per primitive.Eric Anholt2011-06-202-0/+7
* i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.Eric Anholt2011-06-204-3/+23
* i965/gen6: Factor the PIPE_CONTROL workaround to a separate function.Eric Anholt2011-06-201-8/+21