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path: root/src/mesa/drivers/dri/intel
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* intel: Drop doubly irrelevant code in intelReadBuffers.Eric Anholt2011-05-261-12/+0
* intel: Change FBO validation criteria to accomodate hiz and seprate stencilChad Versace2011-05-251-15/+27
* intel: Fix intel_draw_buffer() to accomodate hiz and separate stencilChad Versace2011-05-251-5/+11
* intel: Add hiz_region to intel_mipmap_treeChad Versace2011-05-253-0/+36
* intel: Refactor the wrapping of textures with renderbuffersChad Versace2011-05-251-7/+8
* intel: Add hiz_region to intel_renderbufferChad Versace2011-05-252-0/+46
* intel: Add is_hiz_depth_format() to intel_contex.vtblChad Versace2011-05-251-0/+4
* intel: Allocate region for separate stencil bufferChad Versace2011-05-251-3/+30
* intel: Change supported texture formats for separate stencilChad Versace2011-05-252-1/+7
* intel: Add flags to intel_context for hiz and separate stencilChad Versace2011-05-252-0/+58
* i965: Add support for rendering to depthbuffer mipmap levels > 0.Eric Anholt2011-05-182-0/+39
* i965: Rename IS_GT1 and IS_GT2 to IS_SNB_GT1 and IS_SNB_GT2.Kenneth Graunke2011-05-181-3/+3
* intel: Recognize new Ivybridge PCI IDs.Kenneth Graunke2011-05-172-2/+22
* intel: Initial IS_GEN7 plumbing.Kenneth Graunke2011-05-173-3/+17
* egl: Add a cursor use bit to MESA_drm_imageKristian Høgsberg2011-05-061-1/+9
* Revert "intel: use throttle ioctl for throttling"Eric Anholt2011-04-273-3/+13
* Squashed commit of the following:Brian Paul2011-04-261-1/+1
* intel: Use tiling for dri2AllocateBuffer implementationKristian Høgsberg2011-04-261-1/+10
* intel: Set gen in intelInitScreen, just copy value in intelInitContextKristian Høgsberg2011-04-263-5/+14
* intel: Use X tiling for DRM EGL ImagesKristian Høgsberg2011-04-261-1/+1
* intel: Add support for ARB_sampler_objects.Eric Anholt2011-04-232-3/+9
* i965: Add support for NV_conditional_render.Eric Anholt2011-04-234-0/+13
* i965: Add support for ARB_texture_compression_rgtc.Eric Anholt2011-04-232-0/+7
* intel: Add support for ARB_color_buffer_float.Eric Anholt2011-04-201-0/+1
* intel: Add support for ARB_texture_float.Eric Anholt2011-04-205-1/+31
* intel: Add support for blit copies of >32bpp formats.Eric Anholt2011-04-201-0/+11
* intel: Add I8 and L8 to intel_mesa_format_to_rb_datatype().Eric Anholt2011-04-181-0/+2
* intel: Use mesa core's R8, RG88, R16, RG1616 RB accessors.Eric Anholt2011-04-181-25/+4
* intel: Use Mesa core's renderbuffer accessors for depth.Eric Anholt2011-04-181-33/+15
* intel: Use _mesa_base_tex_format for FBO texture attachments.Eric Anholt2011-04-181-1/+1
* Merge branch 'arb_sampler_objects'Brian Paul2011-04-112-3/+3
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| * mesa: move sampler state into new gl_sampler_object typeBrian Paul2011-04-102-3/+3
* | intel: Fix ROUND_DOWN_TO macroIan Romanick2011-04-111-3/+27
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* dri: Remove driver date from renderer stringIan Romanick2011-04-051-5/+1
* i965: Add the missing supportable EXT_texture_snorm formatsIan Romanick2011-04-041-0/+5
* intel: Fix regression in clear_with_blit from 7bae1c3dChris Wilson2011-03-311-11/+12
* intel: Remove the unrelaxed relocation assertionChris Wilson2011-03-301-4/+0
* intel: Add some defense against buffer allocation failure for subimage blitsChris Wilson2011-03-301-1/+9
* Revert "intel: Add some defense against buffer allocation failure for subimag...Chris Wilson2011-03-301-11/+11
* intel: Add IS_GT2 macro for recognizing Sandybridge GT2 systems.Kenneth Graunke2011-03-291-8/+7
* intel: Protect intel_clear_with_blit from failed buffer allocationsChris Wilson2011-03-291-10/+11
* intel: Don't leak the tex object miptree when replacing itIan Romanick2011-03-281-1/+3
* mesa: replace NEED_SECONDARY_COLOR(), RGBA_LOGICOP_ENABLED() with inlinesBrian Paul2011-03-111-1/+1
* intel: Don't complain when getparam fails due to a missing param.Eric Anholt2011-03-091-1/+3
* intel: check for miptree allocation failureChris Wilson2011-03-071-0/+2
* intel: Add some defense against buffer allocation failure for subimage blitsChris Wilson2011-03-071-11/+11
* intel: Add some defense against bo allocation failureChris Wilson2011-03-071-7/+11
* i965: Align index to type size and flush if the type changesChris Wilson2011-03-043-4/+6
* intel: Add couple of missing gen6 commands to decodeChris Wilson2011-03-041-0/+2
* i965: SNB GT1 has only 32k urb and max 128 urb entries.Zou Nan hai2011-03-031-0/+4
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