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* i965: fixup W-tile offset computation to take swizzling into accountDaniel Vetter2012-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's even a comment in the code containing the right swizzling computations! Previously this has not been noticed because we need to manually enabled swizzling on snb/ivb (kernel 3.4 will do that) and we don't use the separate stencil on ilk (where the bios enables swizzling). This fixes piglit ./bin/fbo-stencil readpixels GL_DEPTH32F_STENCIL8 -auto on recent drm-intel-next kernels. Also remove the comment about ivb, it's stale now. Swizzling detection is done by allocating a temporary x-tiled buffer object. Unfortunately kernels before v3.2 lie on snb/ivb because they claim that swizzling is enable, but it isn't. The kernel commit that fixes this for backport to pre-v3.2 is commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84 Author: Daniel Vetter <[email protected]> Date: Mon Sep 12 20:49:16 2011 +0200 drm/i915: fix swizzling on gen6+ But if the kernel doesn't lie, this now works on swizzling and not swizzling machines. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: remove intel_span_supports_format()Brian Paul2012-01-241-1/+0
| | | | It always returned True.
* intel: make intel_renderbuffer_map/unmap() staticBrian Paul2012-01-241-4/+1
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* intel: Add an implementation of MapRenderbuffer.Eric Anholt2011-11-011-0/+1
| | | | | | | | | v2: Add separate stencil S8 W-tile swizzling/deswizzling. Tested for the swizzling case with env INTEL_SEPARATE_STENCIL=1 INTEL_HIZ=1 ./bin/hiz-depth-stencil-test-fbo-d24-s8 v3: Apply Chad's fix for S8 window system buffers. Reviewed-by: Chad Versace <[email protected]>
* intel: Add a couple of helper functions to reduce rb code duplication.Eric Anholt2010-12-101-0/+4
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* Drop GLcontext typedef and use struct gl_context insteadKristian Høgsberg2010-10-131-5/+5
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* i915: Enable ARB_vertex_shader for both i915 and i830.Eric Anholt2009-10-011-0/+2
| | | | | | Since the TNL is all done in software anyway, it should be the same to the user who's probably using ARB_vertex_program otherwise, but gives them a nicer programming environment.
* Revert "Revert "Merge branch 'drm-gem'""Dave Airlie2008-08-241-2/+4
| | | | This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
* Revert "Merge branch 'drm-gem'"Dave Airlie2008-08-241-4/+2
| | | | | | | | This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
* intel: move renderbuffer mapping to separate functions.Eric Anholt2008-07-231-0/+4
| | | | | | | This lets us avoid duplicated code for doing so, including the depthstencil paths that aren't covered by SpanRenderStart/Finish. Those paths were missing the span funcs setup, leading to a null dereference in the fbotexture demo.
* drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt2008-07-111-3/+0
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* intel-gem: Fix Y-tiling span setup.Eric Anholt2008-07-021-5/+2
| | | | | | | | | The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
* [intel-GEM] Add tiling support to swrast.Keith Packard2008-05-061-1/+5
| | | | | Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself.
* [intel] Move over files that will be shared with 965-fbo work.Eric Anholt2007-11-091-0/+38
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