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* Revert "Revert "Merge branch 'drm-gem'""Dave Airlie2008-08-241-2/+4
| | | | This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
* Revert "Merge branch 'drm-gem'"Dave Airlie2008-08-241-4/+2
| | | | | | | | This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
* intel: move renderbuffer mapping to separate functions.Eric Anholt2008-07-231-0/+4
| | | | | | | This lets us avoid duplicated code for doing so, including the depthstencil paths that aren't covered by SpanRenderStart/Finish. Those paths were missing the span funcs setup, leading to a null dereference in the fbotexture demo.
* drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt2008-07-111-3/+0
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* intel-gem: Fix Y-tiling span setup.Eric Anholt2008-07-021-5/+2
| | | | | | | | | The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
* [intel-GEM] Add tiling support to swrast.Keith Packard2008-05-061-1/+5
| | | | | Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself.
* [intel] Move over files that will be shared with 965-fbo work.Eric Anholt2007-11-091-0/+38