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path: root/src/mesa/drivers/dri/intel/intel_span.c
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* Merge branch 'drm-gem'Eric Anholt2008-08-081-135/+541
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| * intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.Eric Anholt2008-07-261-0/+64
| * intel: Add a little span cache to spead up readpixels by cutting syscalls.Eric Anholt2008-07-231-12/+36
| * intel-gem: Use pread/pwrite for span access.Eric Anholt2008-07-231-161/+111
| * intel: move renderbuffer mapping to separate functions.Eric Anholt2008-07-231-52/+51
| * intel-gem: Disable spantmp sse/mmx functions when tile swizzling.Eric Anholt2008-07-151-0/+4
| * drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt2008-07-111-76/+78
| * intel: span rendering requires just a flush before starting, not finish.Eric Anholt2008-07-021-1/+1
| * intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.Eric Anholt2008-07-021-0/+10
| * intel-gem: Fix Y-tiling span setup.Eric Anholt2008-07-021-3/+4
| * intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt2008-07-011-17/+34
| * [intel-gem] Bug #16326: Fix X tile unswizzling on 965.Eric Anholt2008-06-171-0/+26
| * [intel-GEM] Add tiling support to swrast.Keith Packard2008-05-061-12/+315
* | dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646Xiang, Haihao2008-08-051-1/+4
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* i965: fix segfault caused by commit e131c46b20241737ceba4856dbe01dcca6dd2c03.Xiang, Haihao2008-01-101-6/+6
* Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.Brian2008-01-061-15/+12
* [intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt2007-12-121-12/+12
* [intel] Move over files that will be shared with 965-fbo work.Eric Anholt2007-11-091-0/+409
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