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* intel: Fix segfault in glXSwapBuffers with no bound contextAnuj Phogat2012-01-161-5/+7
| | | | | | | | | | | | | | Calling glXSwapBuffers with no bound context causes segmentation fault in function intelDRI2Flush. All the gl calls should be ignored after setting the current context to null. So the contents of framebuffer stay unchanged. But the driver should not seg fault. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44614 Reported-by: Yi Sun <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Yi Sun <[email protected]>
* i965: Fix compiler warning from uninitialized "success" value.Eric Anholt2012-01-111-1/+1
| | | | | This shouldn't happen, because the DDX should only load this driver if IS_965. But better to do something defined in that case.
* i965/gen7: Enable HiZChad Versace2012-01-101-1/+1
| | | | | | | | | | | | | | | | This patch modifies all batches needed for HiZ. The batch length for 3DSTATE_HIER_DEPTH_BUFFER is also corrected from 4 to 3. Performance +6.7% on Citybench. num-frames: 400 resolution: 1918x1031 avg-hiz-off: 127.90 fps avg-hiz-on: 136.50 fps kernel: git://people.freedesktop.org/~anholt/linux.git branch=gen7-reset-sol sha=23360e4 Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/gen7: Enable transform feedback as long as kernel support is present.Eric Anholt2012-01-061-0/+4
| | | | | | | | | The last major issue (intervening-read) is fixed, so let's turn this on for real. The only other known issue is a hardware limitation for tesselation with flat shading. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eugeni Dodonov <[email protected]>
* intel: include version.h in intel_screen.c to silence warningBrian Paul2012-01-021-0/+1
| | | | Signed-off-by: Brian Paul <[email protected]>
* dri2: Add plumbing to get context version requirements and flags to driversIan Romanick2012-01-021-6/+31
| | | | | | This adds support for DRI_DRI2 version 3 to all of the DRI2 drivers. Signed-off-by: Ian Romanick <[email protected]>
* mesa/drivers: use new swrast renderbuffer functionsBrian Paul2011-12-081-7/+8
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Don't perform the precompile on fragment shaders by default.Eric Anholt2011-11-301-1/+5
| | | | | | | | | | | | | | | | It is useful to have this option for shader-db, and it was also good at the time where we were rejecting shaders due to various internal limits we hadn't supported yet. However, at this point the precompile step takes extra time (since not all NOS is known at link time) and spews misleading debug in the common case of debugging a real app. This is left in place for VS, where we still have a couple of codegen failure paths that result in link failure through precompile. Those need to be fixed. shader-db can still get at the debug info it wants using "shader_precompile=true" driconf option. Long term, we can probably build a good-enough app for shader-db to trigger real codegen.
* i965/gen6: Enable HiZ by defaultChad Versace2011-11-221-6/+2
| | | | | | | | | | Regresses one Piglit test: bugs/fdo10370. I'm not enabling HiZ for gen7 yet because it causes a mysterious performance regression. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Replace intel_renderbuffer::region with a miptree [v3]Chad Versace2011-11-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Essentially, this patch just globally substitutes `irb->region` with `irb->mt->region` and then does some minor cleanups to avoid segfaults and other problems. This is in preparation for 1. Fixing scatter/gather for mipmapped separate stencil textures. 2. Supporting HiZ for mipmapped depth textures. As a nice benefit, this lays down some preliminary groundwork for easily texturing from any renderbuffer, even those of the window system. A future commit will replace intel_mipmap_tree::hiz_region with a miptree. v2: - Return early in intel_process_dri2_buffer_*() if region allocation fails. - Fix double semicolon. - Fix miptree reference leaks in the following functions: intel_process_dri2_buffer_with_separate_stencil() intel_image_target_renderbuffer_storage() v3: - [anholt] Fix check for hiz allocation failure. Replace ``if (!irb->mt)` with ``if(!irb->mt->hiz_region)``. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Fix separate stencil in builtin DRI2 backendChad Versace2011-11-151-9/+80
| | | | | | | | | | | | | | | | intelAllocateBuffer() was oblivious to separate stencil buffers. This patch fixes it to allocate a non-tiled stencil buffer with special pitch, just as the DDX does. Without this, any app that attempted to create an EGL surface with stencil bits would crash. Of course, this affected only environments that used the builtin DRI2 backend, such as Android and Wayland. Fixes GLBenchmark2.1 on Android on gen7. Note: This is a candidate for the 7.11 branch. Tested-by: Louie Tsaie <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* dri: unify __DRIscreenRecGeorge Sapountzis2011-11-041-8/+8
| | | | | Also drop DriverAPI field, this is a static symbol and I don't see why it should be accessed through __DRIscreenRec
* dri: unify __DriverAPIRecGeorge Sapountzis2011-11-041-1/+1
| | | | I dropped the comments because they don't add much.
* dri: Drop driReadDrawableExtensionKristian Høgsberg2011-11-021-1/+0
| | | | All DRI2 drivers support setting a separate read drawable.
* intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke2011-10-181-41/+44
| | | | | | | | | | | | | | | | | I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chad Versace <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Rename region->buffer to region->bo, and remove accessor function.Eric Anholt2011-09-261-1/+1
| | | | | | | We call all the other drm_intel_bo pointers in intel/*.h "bo", so this one was rather out of place. Acked-by: Kenneth Graunke <[email protected]>
* intel: add support for __DRI_IMAGE_FORMAT_ABGR8888Chia-I Wu2011-09-091-0/+10
| | | | | | | | | | | It maps to MESA_FORMAT_RGBA8888_REV. Surfaces of the format can only be sampled from but not render to. Only i915 is tested. Reviewed-by: Eric Anholt <[email protected]> [olv: add a check in intel_image_target_renderbuffer_storage]
* intel: Rely on intel_region_reference()'s support of *dst != NULL.Eric Anholt2011-07-071-1/+0
| | | | Reviewed-by: Chad Versace <[email protected]>
* intel: Implement DRIimageExtension::dupImageBenjamin Franzke2011-06-231-1/+26
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* intel: Request DRI2 buffers for separate stencil and hizChad Versace2011-06-081-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When it is sensible to do so, 1) intelCreateBuffer() now attaches separate depth and stencil buffers to the framebuffer it creates. 2) intel_update_renderbuffers() requests for the framebuffer a separate stencil buffer (DRI2BufferStencil). The criteria for "sensible" is: - The GLX config has nonzero depth and stencil bits. - The hardware supports separate stencil. - The X driver supports separate stencil, or its support has not yet been determined. If the hardware supports hiz too, then intel_update_renderbuffers() also requests DRI2BufferHiz. If after requesting DRI2BufferStencil we determine that X driver did not actually support separate stencil, we clean up the mistake and never ask for DRI2BufferStencil again. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add assertions to intelCreateBuffer()Chad Versace2011-06-081-3/+12
| | | | | | | | | | | | | | | Assert that the GLX config has an expected depth/stencil bit combination: one of d24/s8, d16/s0, d0/s0. These are the only depth/stencil configurations that we advertise. Remove the check for software stencil, because given the assertions' constraints the check always fails. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add flags to intel_screen for hiz and separate stencilChad Versace2011-06-081-0/+60
| | | | | | | | | | | | | | | | | | | | | Add the fields below to intel_screen. The expression in parens is the value to which intelInitScreen2() currently sets the field. GLboolean hw_has_separate_stencil (true iff gen >= 7) GLboolean hw_must_use_separate_stencil (true iff gen >= 7) GLboolean hw_has_hiz (always false) enum intel_dri2_has_hiz dri2_has_hiz (INTEL_DRI2_HAS_HIZ_UNKNOWN) The analogous fields in intel_context now inherit their values from intel_screen. When hiz and separate stencil become completely implemented for a given chipset, then the respective fields need to be enabled. CC: Ian Romanick <[email protected]> CC: Kristian Høgsberg <[email protected]> Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Initial IS_GEN7 plumbing.Kenneth Graunke2011-05-171-1/+3
| | | | | | | | | Currently, IS_GEN7, IS_IVYBRIDGE, IS_IVB_GT1, and IS_IVB_GT2 all return false. This allows me to write the code for them before actually adding the PCI IDs and thus enabling the hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* egl: Add a cursor use bit to MESA_drm_imageKristian Høgsberg2011-05-061-1/+9
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* intel: Use tiling for dri2AllocateBuffer implementationKristian Høgsberg2011-04-261-1/+10
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* intel: Set gen in intelInitScreen, just copy value in intelInitContextKristian Høgsberg2011-04-261-0/+12
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* intel: Use X tiling for DRM EGL ImagesKristian Høgsberg2011-04-261-1/+1
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* intel: Don't complain when getparam fails due to a missing param.Eric Anholt2011-03-091-1/+3
| | | | | This is an expected behavior when we're testing for the presence of new kernel features.
* i965: Use negative relocation deltas to minimse vertex uploadsChris Wilson2011-03-011-0/+11
| | | | | | | | | | | | With relaxed relocation checking in the kernel, we can specify a negative delta (i.e. pointing outside of the target bo) in order to fake a range in a large buffer. We only then need to upload the elements used and adjust the buffer offset such that they correspond with the indices used in the DrawArrays. (Depends on libdrm 0209428b3918c4336018da9293cdcbf7f8fedfb6) Signed-off-by: Chris Wilson <[email protected]>
* intel: Use the current context rather than last bound context for a drawable.Eric Anholt2011-02-261-1/+2
| | | | | | | | If another thread bound a context to the drawable then unbound it, the driContextPriv would end up NULL. With the previous two fixes, this fixes glx-multithread-makecurrent-2, despite the issue not being about the multithreaded makecurrent.
* intel: use pwrite for batchChris Wilson2011-02-211-2/+2
| | | | | | | | | | | It's faster. Not only is the memcpy more efficiently performed in the kernel (making up for the system call overhead), but by not using mmap we remove the greater overhead of tracking the vma of every batch. And it means we can read back from the batch buffer without incurring the cost of a uncached read through the GTT. Signed-off-by: Chris Wilson <[email protected]>
* intel: Implement dri2::{Allocate,Release}BufferBenjamin Franzke2011-02-071-0/+47
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* intel: Include mfeatures.h in files that perform feature tests.Vinson Lee2011-01-091-0/+1
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* intel: Include stdbool so we can stop using GLboolean when we want to.Eric Anholt2010-12-131-13/+11
| | | | | This requires shuffling the driconf XML macros around, since they use true and false tokens expecting them to not get expanded to anything.
* intel: Add an env var override to execute for a different GPU revision.Eric Anholt2010-12-041-2/+14
| | | | | | | Sometimes I'm on the train and want to just read what's generated under INTEL_DEBUG=vs,wm for some code on another generation. Or, for the next gen enablement we'll want to dump aub files before we have the actual hardware. This will let us do that.
* Rename GLvisual and __GLcontextModes to struct gl_configKristian Høgsberg2010-10-131-6/+6
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* intel: Dead comment removal.Eric Anholt2010-09-241-1/+0
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* dri2: Make createImageFromName() take a __DRIscreen instead of __DRIcontextKristian Høgsberg2010-09-221-3/+3
| | | | | | | We can't expect to have a context when this is called, and we don't need one so just require a __DRIscreen instead. Reported by Yu Dai <[email protected]>
* intel: Support EGL_MESA_image_drmKristian Høgsberg2010-08-251-0/+68
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* intel: Take an intel_screen pointer in intel_alloc_region_* functionsKristian Høgsberg2010-08-251-1/+2
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* i915: Enable ARB_fragment_shader by default.Eric Anholt2010-08-171-1/+1
| | | | | | | | | | | | | | | | Now that we have glsl2 with if flattening in place, most shaders will just work. Remaining failing shaders will mostly be due to loop unrolling (in progress), some possible if flattening failures in inlining functions (planning on fixing), and the register/instruction count limits. While the GLSL and GLSL-ES specs say that shaders shouldn't fail to compile/link due to register/instruction limits, in practice we're not the first vendor to expose GLSL on hardware with these limitations. The benefit to application developers of providing a better language for GPU programming is greater than the pain of having to handle instruction limits (which they had to for ARB_fp on this hardware anyway)
* intel: Throttle after doing copyregion/swapbuffers round tripKristian Høgsberg2010-05-201-10/+3
| | | | | | | | | | | Before we would throttle in the flush callback prior to round-tripping to the server to do copyregion or swapbuffer. Now, instead just note that we need to throttle and do it in intel_prepare_render(), which will be called after receiving the response from the server but before we start rendering the next frame. Even if the server also throttles us in swapbuffer, this just makes the throttling a no-op when we hit intel_prepare_render(). With that we can drop the using_dri2_swapbuffers hack and just always throttle.
* Merge branch 'gles2-2'Kristian Høgsberg2010-05-021-5/+21
|\ | | | | | | | | Conflicts: src/mesa/drivers/dri/common/dri_util.h
| * intel: Advertise GLES1/2 for i915+ when enabledKristian Høgsberg2010-04-281-0/+12
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| * dri: Add DRI entrypoints to create a context for a given APIKristian Høgsberg2010-04-281-4/+7
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| * dri: Add DRI entrypoints to create a context for a given APIKristian Høgsberg2010-04-281-1/+2
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* | DRI2: add config query extensionJesse Barnes2010-04-221-0/+1
|/ | | | | Add a new DRI2 configuration query extension. Allows for DRI2 client code to query for common DRI2 configuration options.
* intel: Remove more code for x8z24 visuals, since we only do s8z24.Eric Anholt2010-03-161-12/+7
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* intel: Remove support for the DRI1 TFP extension.Eric Anholt2010-03-051-6/+0
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* intel: Remove non-kernel-exec-fencing support.Eric Anholt2010-03-041-4/+5
| | | | | | | Shaves 60k off the driver from removing the broken spans code. This means we now require 2.6.29, which seems fair given that it's a year old and we've removed support for non-KMS already in the last release of 2D.
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