| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
| |
Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL,
which needs a handle, and failing. None of our buffers were tiled yet, but
they will be at some point with DRI2 and UXA.
|
| | |
|
| |
|
|
|
| |
Otherwise, we would use the pitch as width of the texture, and compiz would
render the pitch padding on the right hand side.
|
| | |
|
| | |
|
| |
|
|
| |
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
|
| |
|
|
|
|
|
|
| |
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| | |
|
| | |
|
| |
|
|
|
| |
This was broken in the merge of 965 blit support. It tried to lock only
when things were already locked.
|
| |
|
|
|
|
|
|
|
| |
Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH. Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
|
| | |
|
| |
|
|
|
|
|
| |
Fencing was used in two places: ensuring that we didn't get too many frames
ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on
buffers like we would do for CPU access on them. The "don't get too far ahead"
is now the responsibility of the execution manager (kernel).
|
| | |
|
| | |
|
| |
|
|
|
|
| |
In addition to potentially binding when it was about to be mapped anyway,
failure to use CACHED_MAPPED means eating a full wbinvd on validate. Thanks to
airlied for catching this.
|
| |
|
|
| |
this fix bad texture issue in some games(UT and quake).
|
| |
|
|
|
|
| |
The screen wide info such as pitch and cpp are obsoleted by the FBO
changes, so clean up the last few references to those, except for
setting up the legacy screen regions.
|
| |
|
|
|
| |
965 gains fixed TTM typing of the buffer object buffers and unused PBO
functions, and 915 gains buffer size == 0 fixes from 965.
|
| |
|
|
|
| |
This adds (so far) unused PBO functions, and holding the lock while writing
to regions (which may be shared static screen regions).
|
| |
|
|
|
| |
The idling it was trying to ensure was covered by the
intel_miptree_image_map()->intel_region_map() that immediately followed it.
|
| |
|
|
|
|
|
|
| |
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
|
| |
|
|
|
| |
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
|
| | |
|
| |
|
