mesa.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	i965: Go back to using the kernel SOL reset feature.	Kenneth Graunke	2013-05-23	1	-0/+4
*	i965: Stop using the kernel SOL reset feature.	Kenneth Graunke	2013-05-21	1	-4/+0
*	intel: Use a CPU map of the batch on LLC-sharing architectures.	Eric Anholt	2013-01-29	1	-6/+20
*	intel: Mark some file-local code as static.	Eric Anholt	2012-09-27	1	-1/+4
*	intel: Move finish_batch() call before MI_BATCH_BUFFER_END and padding.	Kenneth Graunke	2012-08-12	1	-3/+3
*	intel: Make the length for PIPE_CONTROL explicit.	Kenneth Graunke	2012-08-08	1	-8/+8
*	i965: Add hardware context support.	Kenneth Graunke	2012-07-10	1	-2/+7
*	i965: Completely annotate the batch bo when aub dumping.	Paul Berry	2012-05-22	1	-1/+4
*	i965: Emit Ivybridge VS workaround flushes.	Kenneth Graunke	2012-02-15	1	-2/+24
*	intel: Remove num_mapped_regions assertion from _intel_batchbuffer_flush	Ian Romanick	2012-02-07	1	-7/+0
*	intel: Use libdrm's decode functionality instead of the gpu-tools copy.	Eric Anholt	2012-01-30	1	-11/+41
*	i965/gen7: Use the updated interface for SO write pointer resetting.	Eric Anholt	2012-01-06	1	-4/+9
*	i965 Gen6+: Invalidate VF address-based cache on flush	Paul Berry	2011-12-23	1	-0/+1
*	i965 gen6+: Make intel_batchbuffer_emit_mi_flush() actually flush.	Paul Berry	2011-12-20	1	-1/+2
*	intel: Return error value from intel_batchbuffer_flush().	Eric Anholt	2011-10-29	1	-4/+10
*	intel: Add an interface for saving/restoring the batchbuffer state.	Eric Anholt	2011-10-29	1	-0/+21
*	i915: Move the always_flush_cache code to triangle emit.	Eric Anholt	2011-10-29	1	-4/+0
*	intel: Convert from GLboolean to 'bool' from stdbool.h.	Kenneth Graunke	2011-10-18	1	-5/+5
*	intel: Assert that no batch is emitted if a region is mapped	Chad Versace	2011-10-11	1	-0/+7
*	i965: Emit depth stalls and flushes before changing depth state on Gen6+.	Kenneth Graunke	2011-09-26	1	-0/+39
*	Change strerror(ret) to strerror(-ret).	Eugeni Dodonov	2011-09-15	1	-1/+1
*	intel: fix build error	Yuanhan Liu	2011-09-03	1	-1/+1
*	intel: Give an explanation why we are exiting for debugging.	Eugeni Dodonov	2011-09-02	1	-0/+1
*	intel: Upload batchbuffer contents even if INTEL_NO_HW is set.	Eric Anholt	2011-09-02	1	-8/+8
*	i965: Emit texture cache flushes on gen6 along with render cache flushes.	Eric Anholt	2011-07-25	1	-0/+1
*	i965: Enable the PIPE_CONTROL workaround workaround out of paranoia.	Eric Anholt	2011-07-20	1	-3/+28
*	i965: Avoid kernel BUG_ON if we happen to wait on the pipe_control w/a BO.	Eric Anholt	2011-07-20	1	-1/+1
*	intel: Use the post-execution batchbuffer contents for dumping.	Eric Anholt	2011-07-18	1	-1/+3
*	i965/gen6: Apply documented workaround for nonpipelined state packets.	Eric Anholt	2011-06-20	1	-1/+21
*	i965/gen6: Limit the workaround flush to once per primitive.	Eric Anholt	2011-06-20	1	-0/+5
*	i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.	Eric Anholt	2011-06-20	1	-1/+19
*	i965/gen6: Factor the PIPE_CONTROL workaround to a separate function.	Eric Anholt	2011-06-20	1	-8/+21
*	intel: Implement glFinish() correctly by waiting on all previous rendering.	Eric Anholt	2011-06-07	1	-3/+6
*	Revert "intel: use throttle ioctl for throttling"	Eric Anholt	2011-04-27	1	-0/+5
*	intel: Remove the unrelaxed relocation assertion	Chris Wilson	2011-03-30	1	-4/+0
*	intel: use throttle ioctl for throttling	Chris Wilson	2011-02-21	1	-5/+0
*	i965: Move repeat-instruction-suppression to batchbuffer core	Chris Wilson	2011-02-21	1	-2/+66
*	intel: use pwrite for batch	Chris Wilson	2011-02-21	1	-108/+58
*	intel: Buffered upload	Chris Wilson	2011-02-21	1	-5/+2
*	intel: Pack dynamic draws together	Chris Wilson	2011-02-21	1	-0/+6
*	i965: Use MI_FLUSH_DW for blt ring flush on sandybridge	Zhenyu Wang	2010-12-23	1	-2/+5
*	i965: Add support for using the BLT ring on gen6.	Eric Anholt	2010-12-13	1	-20/+35
*	intel: Add an env var override to execute for a different GPU revision.	Eric Anholt	2010-12-04	1	-1/+1
*	intel: Annotate debug printout checks with unlikely().	Eric Anholt	2010-11-03	1	-3/+3
*	intel: For batch, use GTT mapping instead of writing to a malloc and copying.	Eric Anholt	2010-11-02	1	-11/+9
*	i965: sandybridge pipe control workaround before write cache flush	Zhenyu Wang	2010-09-28	1	-1/+9
*	intel: Update intel_decode.c from intel-gpu-tools.	Eric Anholt	2010-07-08	1	-1/+1
*	i965: Add support for streaming indirect state rather than caching objects.	Eric Anholt	2010-06-11	1	-0/+7
*	intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.	Eric Anholt	2010-06-08	1	-2/+3
*	intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.	Eric Anholt	2010-06-08	1	-12/+14