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* i965/blorp: Add support for layered renderingTopi Pohjolainen2015-04-304-5/+9
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Allow blend state to be set for multiple render targetsTopi Pohjolainen2015-04-303-19/+18
| | | | | | | | | | | Original blorp writes only one buffer per shader invocation. Once the launch mechanism is shared with glsl-based programs there will be need for supporting multiple render targets. Also drop the always constant color write disable settings. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Prepare for attributes other than render positionTopi Pohjolainen2015-04-304-7/+12
| | | | | | | | | | | | | | | Note that the magic number of one in gen7 logic is replaced by BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity. On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET) has no effect for native blorp as blorp doesn't use any additional attributes. In fact, regular pipeline setup always uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional attributes. Hence the change makes the two (blorp and regular) consistent. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Remove unused argumentsTopi Pohjolainen2015-04-303-21/+12
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen7/blorp: Remove unused argumentsTopi Pohjolainen2015-04-301-47/+28
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Allow caller to provide sampler settingsTopi Pohjolainen2015-04-303-8/+14
| | | | | | | v2 (Ken): s/use_unorm_coords/non_normalized_coords/ Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Refactor vertex buffer state setupTopi Pohjolainen2015-04-301-26/+34
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Remove constant parameterTopi Pohjolainen2015-04-303-20/+0
| | | | | | | | This was still needed when we had support for blorp clears but now this is fixed to nop. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen8: Expose state base address setupTopi Pohjolainen2015-04-302-2/+5
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/ps/gen8: Refactor state uploadingTopi Pohjolainen2015-04-302-26/+58
| | | | | | | | | v2: Use SET_FIELD() for sampler count, and for that reason added GEN7_PS_SAMPLER_COUNT_MASK. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/ps/gen7: Refactor state uploadingTopi Pohjolainen2015-04-302-20/+45
| | | | | | | | | | | Now the uploading depends only on the input parameters instead of consulting the current gl-state. v2: Rebased on top of sampler count clamping Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Refactor sampler state setupTopi Pohjolainen2015-04-302-22/+47
| | | | | | | | v2 (Matt): Moved * to the name. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Remove dependency to tex object in default color setupTopi Pohjolainen2015-04-301-11/+11
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Refactor and expose brw_upload_binding_table()Topi Pohjolainen2015-04-302-7/+21
| | | | | | | | | | | | Read and write parts of the state stage are also split into explicit arguments allowing future patches to use constant program data. v2 (Ken): s/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/ Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Expose and refactor brw_update_renderbuffer_surfaces()Topi Pohjolainen2015-04-302-21/+35
| | | | | | | | | | Note that brw_update_renderbuffer_surfaces() already had a helper variable which was used in parallel to direct access of the current draw buffer of the context. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Refactor rb surface setup to allow caller to store offsetsTopi Pohjolainen2015-04-305-58/+59
| | | | | | | | | | | Notice that in gen7_wm_surface_state.c there is also indentation change in the surrounding code removing tabs. v2 (Matt): Fixed whitespace: tabs -> spaces Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen8: Use constant pointers for reading miptree detailsTopi Pohjolainen2015-04-301-2/+2
| | | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/ps: Use SET_FIELD() for sampler countTopi Pohjolainen2015-04-303-4/+7
| | | | | | | | The value is actually clamped to 0-16 as sample state pointer can be used to support more than 16 samplers. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Don't try to apply the opt_sampler_eot extension for vsNeil Roberts2015-04-291-0/+3
| | | | | | | | | | | | | | | | | | | The opt_sampler_eot optimisation of fs_visitor effectively assumes that it is running on a fragment shader because it casts the program key to a brw_wm_prog_key. However on Skylake fs_visitor can also be used for vertex shaders. It looks like this usually works anyway because the optimisation is skipped if key->nr_color_regions != 1. However for a vertex shader the key is actually a brw_vs_prog_key so the space for nr_color_regions is probably taken up by key->base.program_string_id. This can end up making nr_color_regions be 1 in which case the function will later assert when the last instruction is not FS_OPCODE_FB_WRITE. This was making the DEQP test suite assert. Presumably this only happens there because that compiles a lot of shaders so it would end up with a high value for program_string_id. Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Remove unnecessary NULL check on generate_code() result.Kenneth Graunke2015-04-271-2/+1
| | | | | | | | | Code generation is not allowed to fail for any reason - in fact, fs_generator has no mechanism for failing. The visitor is responsible for that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Enable ARB_gpu_shader5 on Gen8+.Matt Turner2015-04-271-6/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix code emission for imul_high in NIR.Matt Turner2015-04-271-1/+23
| | | | | | Copy over from brw_fs_visitor.cpp. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix stride for multiply in macro.Matt Turner2015-04-271-0/+2
| | | | | | | | We have to use W/UW type for src1 of the multiply in the MUL/MACH macro, but in order to read the low 16-bits of each 32-bit integer, we need to set the appropriate stride. Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965/fs: Allow SIMD16 borrow/carry/64-bit multiply on Gen > 7."Matt Turner2015-04-271-3/+3
| | | | | | | | | This reverts commit 9f5e5bd34d8ba48c851b442fb88f742b1ba6a571. I have no idea what made me believe these didn't apply to Gen > 7. They do, and without them we generate bad code that causes failures on Gen 8. Reviewed-by: Kenneth Graunke <[email protected]>
* Fix a few typosZoë Blade2015-04-278-14/+14
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* i965/gen8: Factor out texture surface state set-up from ↵Francisco Jerez2015-04-271-60/+77
| | | | | | | gen8_update_texture_surface(). This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
* i965/gen7: Factor out texture surface state set-up from ↵Francisco Jerez2015-04-272-54/+84
| | | | | | | gen7_update_texture_surface(). This moves most of the surface state set-up logic that can be shared between textures and shader images to a separate function.
* i965: Add helper functions to calculate the slice pitch of an array or 3D ↵Francisco Jerez2015-04-272-40/+84
| | | | miptree.
* i965: Fill out the rest of brw_debug_recompile_sampler_key().Kenneth Graunke2015-04-251-0/+8
| | | | | | | | | | This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs. UMS/IMS differences and Sandybridge textureGather workarounds. Previously, we just flagged them as "Something else". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Disassemble sampler message names on Gen5+.Kenneth Graunke2015-04-251-4/+34
| | | | | | | | | | | | | | | | | | | | | | Previously, sampler messages were decoded as sampler (1, 0, 2, 2) mlen 6 rlen 8 { align1 1H }; I don't know how much time we've collectly wasted trying to read this format. I can never recall which number is the surface index, sampler index, message type, or...whatever that other number is. Figuring out the message name from the numerical code is also painful. Now they decode as: sampler sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; This is easy to read at a glance, and matches the format I used for render target formats. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Disallow constant propagation into POW on Gen 6.Matt Turner2015-04-251-2/+8
| | | | | Fixes assertion failures in three piglit tests on Gen 6 since commit 0087cf23e.
* i965/fs: Add missing pixel_x/y to brw_instruction_name().Matt Turner2015-04-241-0/+5
| | | | Forgotten in commit 529064f6.
* i965/fs: Don't constant propagate into integer math instructions.Matt Turner2015-04-242-3/+5
| | | | | | Constant combining won't promote non-floats, so this isn't safe. Fixes regressions since commit 0087cf23e.
* i965/fs: Allow 2-src math instructions to have immediate src1.Matt Turner2015-04-242-7/+11
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add an INTEL_DEBUG=spill option to test spillingJason Ekstrand2015-04-233-1/+3
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/debug: Use the ull specifier for DEBUG enum definesJason Ekstrand2015-04-231-31/+31
| | | | | | | The INTEL_DEBUG variable is a uint64_t and if we want a enum value higer than 32 bits, you need to use ull. We might as well use it for all of them. Reviewed-by: Matt Turner <[email protected]>
* i965: Disallow linear blits that are not cacheline aligned.Kenneth Graunke2015-04-231-8/+19
| | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. The main user, intel_emit_linear_blit, now handles this properly. But we might also have linear miptrees; just refuse to blit those. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.Kenneth Graunke2015-04-231-8/+14
| | | | | | | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. intel_emit_linear_blit needs to handle blits that are not cacheline aligned, as we use it for arbitrary glBufferSubData calls and subrange mappings. Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst pixel X offset field to represent the unaligned portion, and subtract that from the address so it's cacheline aligned. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* i965/nir: Use the correct offsets when handling register indirectsJason Ekstrand2015-04-221-27/+27
| | | | Reviewed-by: Connor Abbott <[email protected]>
* i965: Add a brw_compiler structure and store the register sets in itJason Ekstrand2015-04-227-97/+120
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Rename brw_compile to brw_codegenJason Ekstrand2015-04-2229-246/+246
| | | | | | | | | | | | This name better matches what it's actually used for. The patch was generated with the following command: for file in *; do sed -i -e s/brw_compile/brw_codegen/g $file done Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Use device_info instead of the context for computing vue mapsJason Ekstrand2015-04-224-7/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Use device_info instead of the context in instruction schedulingJason Ekstrand2015-04-223-14/+13
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Add a devinfo field to backend_visitor and use it for gen checksJason Ekstrand2015-04-2219-221/+225
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Remove remaining uses of ctx->Const.UniformBooleanTrue in visitorsJason Ekstrand2015-04-222-12/+6
| | | | | | | | | | Since commit 2881b123, we have used 0/~0 for representing booleans on all gens. However, we still had a bunch of places in the visitor code where we were still referring to ctx->Const.UniformBooleanTrue. Since this is always ~0, we can just remove them. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Add a devinfo field to the generator and use it for gen checksJason Ekstrand2015-04-222-46/+42
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add a devinfo field to the generator and use it for gen checksJason Ekstrand2015-04-222-59/+58
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/device_info: Add a supports_simd16_3src flagJason Ekstrand2015-04-226-55/+56
| | | | | | | | | | This also involves moving revision checking to screen creation time and passing that into brw_get_device_info so that we can get the right device_info for early versions of SKL. Since the only place we used revision was to check for SIMD16 3-src instruction support, it's safe to remove the revision field from brw_context. Reviewed-by: Matt Turner <[email protected]>
* i965/device_info: Add a HSW_FEATURES macroJason Ekstrand2015-04-221-3/+7
| | | | | | It's basically just a copy of GEN7_FEATURES only with is_haswell set Reviewed-by: Matt Turner <[email protected]>
* i965: Make the annotation code take a device_info instead of a contextJason Ekstrand2015-04-224-10/+14
| | | | Reviewed-by: Matt Turner <[email protected]>
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