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path: root/src/mesa/drivers/dri/i965
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* drivers: don't include texformat.hBrian Paul2009-10-053-3/+0
* mesa: replace gl_texture_format with gl_formatBrian Paul2009-09-302-5/+4
* Merge branch 'mesa_7_6_branch'Brian Paul2009-09-253-18/+5
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| * i965: Clean up some mess with the batch cache.Eric Anholt2009-09-243-18/+5
* | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-243-2/+4
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| * i965: Emit zero initialization for NV VP temporaries as required.Eric Anholt2009-09-241-0/+1
| * i965: Remove assert about NV_vp now that it somewhat works.Eric Anholt2009-09-241-2/+0
| * i965: Load NV program matrices when required.Eric Anholt2009-09-241-0/+3
| * i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-101-1/+1
* | i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt2009-09-115-102/+126
* | i965: Enable loops in the VS.Eric Anholt2009-09-101-15/+38
* | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-091-1/+1
* | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-093-1/+4
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| * Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-093-1/+4
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| | * i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
| | * intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-041-0/+1
| | * intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-041-0/+1
| | * i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| | * intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| | * i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| | * i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
| | * i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
| | * i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-09-041-0/+13
| | * i965: Spell "conditional" correctly.Eric Anholt2009-09-043-15/+15
| | * i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-09-041-1/+5
| | * i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-09-041-0/+14
| | * i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
| | * i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-09-041-1/+8
| | * i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-09-041-0/+22
| | * i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-09-042-29/+18
| | * i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-09-041-1/+1
| | * i965: rename var: s/tmp/vs_inputs/Brian Paul2009-09-041-8/+8
| | * i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled.Eric Anholt2009-07-201-1/+2
| | * i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-07-044-17/+16
| | * i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt2009-07-041-13/+11
| | * i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-221-0/+1
| | * i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-06-171-0/+10
| | * i965: fix segfault on low memory conditionsRobert Ellison2009-06-171-0/+7
| | * i956: Make state dependency of SF on drawbuffer bounds match Mesa's.Eric Anholt2009-06-171-2/+5
| | * i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-06-171-8/+10
| | * i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-06-174-13/+27
* | | intel: Add support for ARB_draw_elements_base_vertex.Eric Anholt2009-09-081-1/+1
* | | i965: Add support for ARB_depth_clamp.Eric Anholt2009-09-082-5/+14
* | | i965: Respect spec requirement for pixel shader computed depth with no zbuffer.Eric Anholt2009-09-081-0/+7
* | | i965: Set NULL WM surfaces as tiled according to requirement by specs.Eric Anholt2009-09-081-1/+1
* | | i965: Use the renderbuffer surface size instead of region size for WM surfaces.Eric Anholt2009-09-081-2/+7
* | | i965: #include clean-upsBrian Paul2009-09-082-8/+4
* | | i965: use _mesa_is_bufferobj()Brian Paul2009-09-081-2/+3
* | | i965: Don't set the complete field when there is more VUE yet to come.Eric Anholt2009-09-041-1/+1
* | | i965: Add support for 2 threads in the GS.Eric Anholt2009-09-041-1/+4
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