| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | vbo: Avoid extra validation of DrawElements. | Eric Anholt | 2009-08-12 | 2 | -38/+16 |
| * | i965: Use _MaxElement instead of index-calculated min/max for VBO bounds. | Eric Anholt | 2009-08-12 | 1 | -2/+3 |
| * | i965: Add a note justifying domain choice for the SF VP. | Eric Anholt | 2009-08-07 | 1 | -0/+3 |
| * | i965: Replace the subroutine-skipping jump in VS with a NOP if it's a NOP. | Eric Anholt | 2009-08-07 | 1 | -1/+5 |
| * | i965: minor context comments | Brian Paul | 2009-08-07 | 1 | -1/+5 |
| * | i965: Fix source depth reg setting for FSes reading and writing to depth. | Eric Anholt | 2009-08-05 | 3 | -1/+5 |
| * | i965: Fix dangerous warning I let slip in. | Eric Anholt | 2009-08-04 | 1 | -1/+1 |
| * | i965: Respect CondSwizzle in OPCODE_IF. | Eric Anholt | 2009-08-04 | 1 | -1/+21 |
| * | i965: Emit conditional code updates as required for GLSL VS if statements. | Eric Anholt | 2009-08-04 | 1 | -0/+13 |
| * | i965: Don't set pop_count in the reserved MBZ area of IF statements. | Eric Anholt | 2009-08-04 | 1 | -1/+1 |
| * | i965: Print out ELSE and ENDIF src1 arguments like IF does. | Eric Anholt | 2009-08-04 | 1 | -2/+2 |
| * | intel: Add support for EXT_provoking_vertex. | Eric Anholt | 2009-08-04 | 1 | -4/+14 |
| * | i965: Spell "conditional" correctly. | Eric Anholt | 2009-08-04 | 3 | -16/+16 |
| * | i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}. | Eric Anholt | 2009-08-04 | 8 | -12/+47 |
| * | i965: Initial import of disasm code from intel-gen4asm. | Eric Anholt | 2009-08-04 | 1 | -0/+901 |
| * | i965: warning fix | Eric Anholt | 2009-08-04 | 1 | -1/+1 |
| * | i965: Fix RECT shadow sampling by not losing the other texcoords. | Eric Anholt | 2009-08-04 | 1 | -1/+5 |
| * | i965: Assert that the offset in the VBO is below the VBO size. | Eric Anholt | 2009-08-03 | 1 | -0/+14 |
| * | i965: Even if no VS inputs are set, still load some amount of URB as required. | Eric Anholt | 2009-08-03 | 1 | -0/+11 |
| * | i965: Make sure the VS URB size is big enough to fit a VF VUE. | Eric Anholt | 2009-08-03 | 1 | -2/+8 |
| * | i965: Don't emit bad packets when no VBs are referenced. | Eric Anholt | 2009-08-03 | 1 | -0/+22 |
| * | i965: Calculate enabled[] and nr_enabled once and re-use the values. | Eric Anholt | 2009-08-03 | 2 | -29/+18 |
| * | Rename TGSI LOOP instruction to better match theri usage. | Michal Krol | 2009-07-31 | 1 | -1/+1 |
| * | i965: Postpone ff_sync message in CLIP kernel on IGDNG | Xiang, Haihao | 2009-07-30 | 6 | -20/+53 |
| * | i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled. | Eric Anholt | 2009-07-20 | 1 | -1/+2 |
| * | i965: Add missing state dependency of sf_unit on _NEW_BUFFERS. | Eric Anholt | 2009-07-16 | 1 | -2/+4 |
| * | i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNG | Xiang, Haihao | 2009-07-15 | 2 | -6/+24 |
| * | i965: add support for new chipsets | Xiang, Haihao | 2009-07-13 | 27 | -130/+762 |
| * | i965: Remove BRW_NEW_INPUT_VARYING | Eric Anholt | 2009-07-07 | 3 | -10/+1 |
| * | i965: fixes for JMPI | Xiang, Haihao | 2009-07-02 | 3 | -10/+14 |
| * | i965: Increase G4X default VS URB allocation to actually allow 32 threads. | Eric Anholt | 2009-06-30 | 1 | -3/+14 |
| * | i965: first attempt at handling URB overflow when there's too many vs outputs | Brian Paul | 2009-06-30 | 2 | -4/+49 |
| * | i965: use BRW_MAX_MRF | Brian Paul | 2009-06-30 | 1 | -1/+1 |
| * | i965: use BRW_MAX_GRF, BRW_MAX_MRF | Brian Paul | 2009-06-30 | 1 | -2/+3 |
| * | i965: move BRW_MAX_GRF, define BRW_MAX_MRF | Brian Paul | 2009-06-30 | 2 | -6/+8 |
| * | i965: defined BRW_MAX_MRF | Brian Paul | 2009-06-30 | 1 | -0/+3 |
| * | i965: comments and a new assertion | Brian Paul | 2009-06-30 | 1 | -2/+4 |
| * | intel: Move note_unlock() implementation to the one place it's needed. | Eric Anholt | 2009-06-29 | 2 | -9/+2 |
| * | i965: fix fetching constants from constant buffer in glsl path | Roland Scheidegger | 2009-06-26 | 4 | -17/+16 |
| * | i965: Set the max index buffer address correctly according to the docs. | Eric Anholt | 2009-06-23 | 1 | -1/+1 |
| * | i965: Don't set a reserved bit in MI_FLUSH. | Eric Anholt | 2009-06-23 | 1 | -1/+1 |
| * | i965: Fix packed depth/stencil textures to be Y-tiled as well. | Eric Anholt | 2009-06-23 | 1 | -0/+2 |
| * | intel: Also get the DRI2 front buffer when doing front buffer reading. | Eric Anholt | 2009-06-19 | 1 | -0/+1 |
| * | intel: Update Mesa state before span setup in glReadPixels. | Eric Anholt | 2009-06-19 | 1 | -0/+1 |
| * | i965: initial code for loops in vertex programs | Brian Paul | 2009-06-19 | 1 | -2/+38 |
| * | i965: asst clean-ups, etc in brw_vs_emit() | Brian Paul | 2009-06-19 | 1 | -11/+10 |
| * | i965: asst clean-ups, var renaming in brw_wm_emit_glsl() | Brian Paul | 2009-06-19 | 1 | -21/+23 |
| * | i965: Add decode for the G4X x,y offset in surface state. | Eric Anholt | 2009-06-17 | 1 | -0/+2 |
| * | i965: Fix up texture layout for small things with wide pitches (tiled) | Eric Anholt | 2009-06-17 | 1 | -1/+1 |
| * | i965: Fall back or appropriately adjust offsets of drawing to tiled regions. | Eric Anholt | 2009-06-17 | 3 | -3/+54 |
