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* i965/gen7+: Implement fast color clear operation in BLORP.Paul Berry2013-06-127-14/+179
| | | | | | | | | | | | | | | | | | Since we defer allocation of the MCS miptree until the time of the fast clear operation, this patch also implements creation of the MCS miptree. In addition, this patch adds the field intel_mipmap_tree::fast_clear_color_value, which holds the most recent fast color clear value, if any. We use it to set the SURFACE_STATE's clear color for render targets. v2: Flag BRW_NEW_SURFACES when allocating the MCS miptree. Generate a perf_debug message if clearing to a color that isn't compatible with fast color clear. Fix "control reaches end of non-void function" build warning. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.Paul Berry2013-06-122-2/+2
| | | | | | | | | | | | | | | On Gen7+, MCS buffers are used both for compressed multisampled color buffers and for "fast clear" of single-sampled color buffers. Previous to this patch series, we didn't support fast clear, so we only used MCS with multisampled bolor buffers. As a first step to implementing fast clears, this patch modifies the code that sets up SURFACE_STATE so that it configures the MCS buffer whenever it is present, regardless of whether we are multisampling or not. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Create an enum for keeping track of fast color clear state.Paul Berry2013-06-124-0/+6
| | | | | | | | | | | | | This patch includes code to update the fast color clear state appropriately when rendering occurs. The state will also need to be updated when a fast clear or a resolve operation is performed; those state updates will be added when the fast clear and resolve operations are added. v2: Create a new function, intel_miptree_used_for_rendering() to handle updating the fast color clear state when rendering occurs. Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit the depth/stencil state pointer directly, not via atoms.Kenneth Graunke2013-06-117-80/+18
| | | | | | | | | | | | | | | | | | | | | See two commits ago for the rationale. This allows us to delete the whole gen7_cc_state.c file. This does move these commands before the depth stall flushes from brw_emit_depthbuffer, which may be a problem. The documentation for 3DSTATE_DEPTH_BUFFER mentions that depth stall flushes are required before changing any depth/stencil buffer state, but explicitly lists 3DSTATE_DEPTH_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER, and 3DSTATE_CLEAR_PARAMS. It does not mention this particular packet (_3DSTATE_DEPTH_STENCIL_STATE_POINTERS). No observed Piglit regressions on Sandybridge or Ivybridge. Together with the last two commits, this makes a cairo-gl benchmark faster by 0.324552% +/- 0.258355% on Ivybridge. No statistically significant change on Sandybridge. (Thanks to Eric for the numbers.) Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Emit the CC state pointer directly rather than via atoms.Kenneth Graunke2013-06-115-30/+18
| | | | | | See the previous commit for the rationale. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Emit the BLEND_STATE pointer directly rather than via atoms.Kenneth Graunke2013-06-115-30/+18
| | | | | | | | | | | | | | | | | | | | | | | | Previously, we would: 1. Emit the new indirect state. 2. Flag CACHE_NEW_BLEND_STATE. 3. Rely on later state atoms to notice CACHE_NEW_BLEND_STATE and emit a pointer to the new indirect state. This is rather cumbersome: it requires two state atoms instead of one, and there's a strict ordering dependency in the list. Plus, the code gets spread across two functions (or even files in the case of Gen7+). Gen7+ has a packet to update just the blend state pointer, so it makes a lot of sense to simply emit that right away. Gen6 has a combined packet which updates blending, the color calculator, and depth/stencil state; however, each can still be modified independently. This drops the Gen6 micro-optimization where we tried to only emit one packet that changed all three states. State updates are pretty cheap. CACHE_NEW_BLEND_STATE is no longer necessary, so drop it. Signed-off-by: Kenneth Graunke <[email protected]>
* Revert "i965: Disable unused pipeline stages once at startup on Gen7+."Kenneth Graunke2013-06-113-6/+13
| | | | | | | | | | This reverts commit 6c966ccf07bcaf64fba1a9b699440c30dc96e732. Apparently causes GPU hangs. Conflicts: src/mesa/drivers/dri/i965/brw_state.h src/mesa/drivers/dri/i965/brw_state_upload.c
* i965/vs: Avoid the MUL/MACH/MOV sequence for small integer multiplies.Eric Anholt2013-06-101-13/+37
| | | | | | | | | | | | | | | We do a lot of multiplies by 3 or 4 for skinning shaders, and we can avoid the sequence if we just move them into the right argument of the MUL. On pre-IVB, this means reliably putting a constant in a position where it can't be constant folded, but that's still better than MUL/MACH/MOV. Improves GLB 2.7 trex performance by 0.788648% +/- 0.23865% (n=29/30) v2: Fix test for pre-sandybridge. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> (v1)
* i965/vs: Allow copy propagation into MUL/MACH.Eric Anholt2013-06-101-2/+4
| | | | | | | | | | | This is a trivial port of 1d6ead38042cc0d1e667d8ff55937c1e32d108b1 from the FS. No significant performance difference on trex (misplaced the data, but it was about n=20). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vs: Use the MAD instruction when possible.Eric Anholt2013-06-104-0/+43
| | | | | | | | | | | | | | This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Allocate push constant L3 space once at startup on Gen7+.Kenneth Graunke2013-06-104-12/+4
| | | | | | | | | | | We always allocate the maximum amount of space and never change it, so it makes sense to do it once. Programming it on startup also lets us skip re-programming it from BLORP. This removes a tiny amount of overhead from our drawing loop. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Disable unused pipeline stages once at startup on Gen7+.Kenneth Graunke2013-06-103-13/+9
| | | | | | | This removes a tiny bit of code from our drawing loop. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Don't emit PIPELINE_SELECT from BLORP.Kenneth Graunke2013-06-101-19/+0
| | | | | | | | | | | Now that we emit invariant state at startup (and never select the media pipeline), the 3D pipeline will always already be selected, even if BLORP is the first operation. So this is unnecessary. v2: Fix unused variable warning (intel_context is no longer used). Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Emit invariant state once at startup on Gen6+.Kenneth Graunke2013-06-103-4/+20
| | | | | | | | | | | Now that we have hardware contexts, we can safely initialize our GPU state once at startup, rather than needing a state atom with the BRW_NEW_CONTEXT flag set. This removes a tiny bit of code from our drawing loop. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Delete some dead state atom prototypes.Kenneth Graunke2013-06-101-9/+0
| | | | | | | These atoms don't actually exist. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Change return type of check_state() to bool.Kenneth Graunke2013-06-101-2/+2
| | | | | | | The existing code already returned a boolean; this just clarifies that. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Remove unused second parameter of brw_print_dirty_count().Kenneth Graunke2013-06-101-4/+4
| | | | | Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vs: add support for emitting gl_ClipVertexChris Forbes2013-06-072-7/+3
| | | | | | | | | | | Removes the special-case suppression of gl_ClipVertex in the VUE map. Also calculate vertex outcodes for user clip planes based on gl_ClipVertex if written; otherwise gl_Position. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/clip: Add support for gl_ClipVertexChris Forbes2013-06-073-4/+55
| | | | | | | | | | | When clipping triangles against a user clip plane, and gl_ClipVertex is provided in the vertex, use it instead of hpos. TODO: A similar change should be made at some point for line clipping. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Don't try to blorp or blit CopyTexSubImage(1D_ARRAY).Paul Berry2013-06-041-0/+6
| | | | | | | | | | | | | | | | Blorp and the hardware blitter can't be used to implement CopyTexSubImage when the image type is 1D_ARRAY, because of a coordinate system mismatch (the Y coordinate in the source image is supposed to be matched up to the Z coordinate in the destination texture). The hardware blitter path (intel_copy_texsubimage) contained a perf debug warning for this case, but it failed to actually fall back. The blorp path didn't even check. Fixes piglit test "copyteximage 1D_ARRAY". Reviewed-by: Eric Anholt <[email protected]>
* i965: fix problem with constant out of bounds access (v3)Dave Airlie2013-06-043-1/+16
| | | | | | | | | | | | | | | | | | | | | | | Okay I now understand why Frank would want to run away, this is my attempt at fixing the CVE out of bounds access to constants outside the range. This attempt converts any illegal constants to constant 0 as per the GL spec, and is undefined behaviour. A future patch should add some debug for users to find this out, but this needs to be backported to stable branches. CVE-2013-1872 v2: drop the last hunk which was a separate fix (now in master). hopefully fix the indentations. v3: don't fail piglit, the whole 8/16 dispatch stuff was over my head, and I spent a while figuring it out, but this one is definitely safe, one piglit pass extra on my Ironlake. NOTE: This is a candidate for stable branches. Signed-off-by: Dave Airlie <[email protected]>
* intel: Fix copying of separate stencil data in glCopyTexSubImage().Eric Anholt2013-06-031-8/+15
| | | | | | | | | | | | | We were copying the source stencil data onto the destination depth data. Fixes piglit copyteximage other than 1D_ARRAY. v2: Fix unintentional dropping of the "don't double-copy for packed depth/stencil" check. While blorp is only supported on separate stencil hardware at the moment, hopefully that will change soon. Review by Jordan. Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix glColorPointer(GL_FIXED)Chad Versace2013-06-031-0/+8
| | | | | | | | | | | | | | | | | | | | | When a gl_client_array is created with glColorPointer, gl_client_array::Normalized is true. This caused the translation from the gl_client_array's type to a BRW_SURFACEFORMAT to assertion fail. Fixes the spinning cube's color in Android 4.2's ApiDemos.apk, "Graphics > OpenGL ES". Fixes assertion failure in mesa-demos/src/egl/opengles1/tri_x11 on Haswell and Ivybridge: brw_draw_upload.c:287: get_surface_type: Assertion `0' failed. No Piglit regressions on Haswell. Note: This is a candidate for the 9.1 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42182 Issue: AXIA-2954 Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965 gen7: use SURFACE_STATE fields to select render level/layerJordan Justen2013-06-022-18/+46
| | | | | | | | | | Rather than pointing the surface_state directly at a single sub-image of the texture for rendering, we now point the surface_state at the top level of the texture, and configure the surface_state as needed based on this. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: add layered parameter to update_renderbuffer_surfaceJordan Justen2013-06-022-1/+8
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix haswell_upload_cut_index when there's no index buffer.Kenneth Graunke2013-05-311-1/+13
| | | | | | | | | | | | | brw->ib.type is reset to -1 at the start of each batch. If there's no index buffer, it won't get updated to a sensible value, resulting in _mesa_primitive_restart_index's "Invalid index buffer type" assertion tripping. Fixes a regression since 7c87a3b5dac118697a9b67caa7b6d5cab60f316d. NOTE: This is a candidate for the 9.1 branch (and should be squashed). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65195 Signed-off-by: Kenneth Graunke <[email protected]>
* intel: Add multisample scaled blitting in blorp engineAnuj Phogat2013-05-303-74/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | In traditional multisampled framebuffer rendering, color samples must be explicitly resolved via BlitFramebuffer before doing the scaled blitting of the framebuffer. So, scaled blitting of a multisample framebuffer takes two separate calls to BlitFramebuffer. This patch implements the functionality of doing multisampled scaled resolve using just one BlitFramebuffer call. Important changes involved in this patch are listed below: - Use float registers to scale and offset texture coordinates. - Change offset computation to consider float coordinates. - Round the scaled coordinates down to nearest integer. - Modify src texture coordinates clipping to account for scaling.. - Linear filter is not yet implemented in blorp. So, don't use blorp engine to do single sampled scaled blitting. V3: Fix nearest filtering issue in scaled blits. Makes failing piglit fbo-blit-stetch test and framebuffer_blit_functionality_magnifying_blit.test in gles3 CTS pass. Observed no piglit, gles3 CTS regressions on sandybridge & ivybridge with this patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* intel: Change the register type from UW to UD in blorp engineAnuj Phogat2013-05-303-52/+90
| | | | | | | | | | These changes are required to implement scaled blitting in blorp in my next patch. No regressions observed in piglit quick-driver.tests with this patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* Revert "i965: fix problem with constant out of bounds access (v2)"Kenneth Graunke2013-05-291-11/+1
| | | | | | | | This reverts commit 98dfd59a0445666060c97b0dccaf0e9f030b547a. The patch was clearly not Piglit tested, as it caused at least 225 tests to start crashing with assertion failures. That was before my desktop tanked and the test run died completely.
* i965: fix problem with constant out of bounds access (v2)Dave Airlie2013-05-301-1/+11
| | | | | | | | | | | | | | | | | | | | This is my attempt at fixing this as the CVE is making RH security team care enough to make me look at this. (please upstream, security fixes are more important than whatever else you are doing, if for no other reason than it saves me having to fix stuff I've no real clue about). Since Frank's original fix was denied, here is my attempt to just alias all constants that are out of bounds < 0 or > nr_params to constant 0, hopefully this provides the undefined behaviour idr requires.. CVE-2013-1872 v2: drop the last hunk which was a separate fix (now in master). hopefully fix the indentations. NOTE: This is a candidate for stable branches. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* intel: initialize fs_visitor::params_remap in constructorFrank Henigman2013-05-301-0/+2
| | | | | | | | | | | | Set fs_visitor::params_remap to NULL in the constructor. This variable was potentially tested in fs_visitor::remove_dead_constants() before being set. NOTE: This is a candidate for stable release branches. Signed-off-by: Frank Henigman <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Fix can_cut_index_handle_restart_index() for byte/short types.Kenneth Graunke2013-05-291-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Pre-Haswell hardware doesn't support an arbitrary restart index, and instead compares the index buffer value against 0xFF for byte-size buffers, 0xFFFF for short-size buffers, or 0xFFFFFFFF for unsigned integer buffers. OpenGL allows the restart index to be an arbitrary unsigned integer. When comparing against byte/short types, the index buffer value should be promoted to a full 32-bit integer before doing the comparison. The restart index is /not/ supposed to be masked to byte/short size. This means that with certain restart indexes, the comparison should always fail. For example, a restart index of 0xF000FFFF should never match any byte/short index buffer values due to the extra high bits. We must not enable hardware primitive restart in such a case. For now, fall back to software primitive restart as it's the simplest fix. In the future, we could detect restart indexes that will never match and skip both hardware and software primitive restart. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Use the correct restart index for fixed index mode on Haswell.Kenneth Graunke2013-05-291-2/+4
| | | | | | | | | | | | | | | | | | | | | | The code that updates the ctx->Array._RestartIndex derived state mashed it to 0xFFFFFFFF when GL_PRIMITIVE_RESTART_FIXED_INDEX was enabled regardless of the index buffer type. It's supposed to be 0xFF for byte, 0xFFFF for short, or 0xFFFFFFFF for integer types. The new _mesa_primitive_restart_index() helper gets this right. The hardware appears to compare against the full 32-bit value some of the time, causing primitive restart not to occur when it should. The fact that it works some of the time is rather frightening. Fixes sporadic failures in the ES 3 instanced_arrays_primitive_restart conformance test when run in combination with other tests. NOTE: This is a candidate for the 9.1 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vs: Fix implied_mrf_writes() for integer division pre-gen6.Eric Anholt2013-05-291-0/+2
| | | | | | | | | | | Previously it would assertion fail in debug builds (though the correct value was returned in a non-debug build). Marking it as a candidate for stable even though it has no current consumers in the stable branches, in case one shows up in a later backport. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64727 NOTE: This is a candidate for stable branches. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix test for smearing enabled on an instruction.Eric Anholt2013-05-291-1/+1
| | | | | | | | | | | | | | | | We were expanding the live range too far, breaking register_coalesce_2() and compute_to_mrf() on 16-wide shaders. Turning it back on improves GLB2.7 performance by 0.239355% +/- 0.0850649% (n=398). shader-db stats are: total instructions in shared programs: 1627211 -> 1609262 (-1.10%) instructions in affected programs: 450351 -> 432402 (-3.99%) While 33 new 16-wide shaders are gained, 70 are lost. Despite that, tropics (the app that lost the most 16-wide) shows a .41% +/- .16% (n=7/8, first-run outlier removed) performance improvement on my HSW. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix segfault in instruction scheduling with LINTERP using last GRF.Eric Anholt2013-05-291-2/+8
| | | | | | | | | The scheduler didn't know about uniform-type accesses, and if a uniform access was last in a 16-wide, we'd walk off the end of the array. This never happened, because we'd never coalesce out all the GRFs, due to a bug to be fixed in the next commit. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Rename intel_renderbuffer_tile_offsets.Eric Anholt2013-05-282-3/+3
| | | | | | | | This makes it more consistent with intel_miptree_get_tile_offsets(). Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Make intel_miptree_get_tile_offsets return a page offset.Eric Anholt2013-05-282-6/+7
| | | | | | | | | Right now, the callers in i965 don't expect a nonzero page offset to actually occur (since that's being handled elsewhere), but it seems like a trap to leave it this way. Reviewed-and-tested-by: Ian Romanick <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Go back to using the kernel SOL reset feature.Kenneth Graunke2013-05-231-8/+2
| | | | | | | | | | | | | | | It turns out the MI_LOAD_REGISTER_IMM approach doesn't work on Haswell, and regressed essentially all the transform feedback Piglit tests. This morally reverts eaa6fbe6d54dc99efac4ab8e800edef65ce8220d. However, the code is still simpler than it was. On BeginTransformFeedback, we simply flush the batch and set the SOL reset flag so that the next batch will start with zeroed offsets. There's still no software counting. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64887 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enable guardband clipping on Gen4/5.Chris Forbes2013-05-241-3/+45
| | | | | | | | | | Enables guardband clipping when the viewport covers the entire render target. No piglit regressions on Ironlake. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Shut up more compiler warnings from vector insert/extract changes.Eric Anholt2013-05-221-0/+8
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split BeginTransformFeedback hook into Gen6 and Gen7+ variants.Kenneth Graunke2013-05-214-29/+42
| | | | | | | | | | | Most of the work in BeginTransformFeedback is only necessary on Gen6. We may as well just skip it on Gen7+. v2: Add an intel->gen == 6 assert. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Kill software primitive counting entirely.Kenneth Graunke2013-05-216-108/+22
| | | | | | | | | | | | | | | | Now that we have hardware contexts, we don't need to continually reprogram the GS_SVBI_INDEX registers. They're automatically saved and restored with the context, so they can just increment over time. We only need to reset them when starting transform feedback. There's also no reason to delay until the next drawing operation; we can just emit the packet immediately. However, this means we must drop the initialization in brw_invariant_state, as BeginTransformFeedback may occur before the first drawing in a context. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove software geometry query code.Kenneth Graunke2013-05-214-71/+0
| | | | | | | | | | EXT_transform_feedback isn't yet supported on Gen4-5, so none of this query code is actually used. This also means we can remove some of the surrounding support code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Delete unused brw->sol.offset_0_batch_start field.Kenneth Graunke2013-05-213-8/+0
| | | | | | | | This was only used for the the non-hardware context code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Stop using the kernel SOL reset feature.Kenneth Graunke2013-05-211-5/+8
| | | | | | | | We can just do it ourselves with MI_LOAD_REGISTER_IMM. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove dead code for Gen7 SOL without hardware contexts.Kenneth Graunke2013-05-211-15/+0
| | | | | | | | | Failing to get a hardware context now means failing to load the driver, so this code will never get hit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Fix build failureAnuj Phogat2013-05-201-0/+1
| | | | | meta.h should be included in brw_state_upload.c to get access to function _mesa_meta_in_progress().
* i965: Implement transform feedback query support in hardware on Gen6+.Kenneth Graunke2013-05-201-35/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have hardware contexts and can use MI_STORE_REGISTER_MEM, we can use the GPU's pipeline statistics counters rather than going out of our way to count primitives in software. Aside from being simpler, this also paves the way for Geometry Shaders, which can output an arbitrary number of primitives on the GPU. It will also allow us to use hardware primitive restart when these queries are in use. The GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN query is easy: it corresponds to the SO_NUM_PRIMS_WRITTEN/SO_NUM_PRIMS_WRITTEN0_IVB counters. The GL_PRIMITIVES_GENERATED query is trickier. Gen provides several statistics registers which /almost/ match the semantics required: - IA_PRIMITIVES_COUNT The number of primitives fetched by the VF or IA (input assembler). This undercounts when GS is enabled, as it can output many primitives. - GS_PRIMITIVES_COUNT The number of primitives output by the GS. Unfortunately, this doesn't increment unless the GS unit is actually enabled, and it usually isn't. - SO_PRIM_STORAGE_NEEDED*_IVB The amount of space needed to write primitives output by transform feedback. These naturally only work when transform feedback is on. We'd also have to add the counters for all four streams. - CL_INVOCATION_COUNT The number of primitives processed by the clipper. This doesn't work if the GS or SOL throw away primitives for rasterizer discard. However, it does increment even if the clipper is in REJECT_ALL mode. Dynamically switching between counters would be painfully complicated, especially since GS, rasterizer discard, and transform feedback can all be switched on and off repeatedly during a single query. The most usable counter is CL_INVOCATION_COUNT. The previous two patches reworked rasterizer discard support so that all primitives hit the clipper, making this work. v2: Occlusion query bug fixes removed and squashed in earlier patches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Handle rasterizer discard in the clipper rather than GS on Gen6.Kenneth Graunke2013-05-204-40/+11
| | | | | | | | | | | | | | | | This has more of a negative impact than the previous patch, as on Gen6 passing primitives through to the clipper means we actually have to make the GS thread write them to the URB. I don't see another good solution though, and rasterizer discard is not the most common of cases, so hopefully it won't be too terrible. v2: Add a perf_debug; resolve rebase conflicts on the brw dirty flags; remove the rasterizer_discard field from brw_gs_prog_key. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Reviewed-by: Paul Berry <[email protected]>
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