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path: root/src/mesa/drivers/dri/i965
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* i965: add support for new chipsetsXiang, Haihao2009-07-1327-130/+762
* i965: Remove BRW_NEW_INPUT_VARYINGEric Anholt2009-07-073-10/+1
* i965: fixes for JMPIXiang, Haihao2009-07-023-10/+14
* i965: Increase G4X default VS URB allocation to actually allow 32 threads.Eric Anholt2009-06-301-3/+14
* i965: first attempt at handling URB overflow when there's too many vs outputsBrian Paul2009-06-302-4/+49
* i965: use BRW_MAX_MRFBrian Paul2009-06-301-1/+1
* i965: use BRW_MAX_GRF, BRW_MAX_MRFBrian Paul2009-06-301-2/+3
* i965: move BRW_MAX_GRF, define BRW_MAX_MRFBrian Paul2009-06-302-6/+8
* i965: defined BRW_MAX_MRFBrian Paul2009-06-301-0/+3
* i965: comments and a new assertionBrian Paul2009-06-301-2/+4
* intel: Move note_unlock() implementation to the one place it's needed.Eric Anholt2009-06-292-9/+2
* i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-06-264-17/+16
* i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-06-231-1/+1
* i965: Don't set a reserved bit in MI_FLUSH.Eric Anholt2009-06-231-1/+1
* i965: Fix packed depth/stencil textures to be Y-tiled as well.Eric Anholt2009-06-231-0/+2
* intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-06-191-0/+1
* intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-06-191-0/+1
* i965: initial code for loops in vertex programsBrian Paul2009-06-191-2/+38
* i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-06-191-11/+10
* i965: asst clean-ups, var renaming in brw_wm_emit_glsl()Brian Paul2009-06-191-21/+23
* i965: Add decode for the G4X x,y offset in surface state.Eric Anholt2009-06-171-0/+2
* i965: Fix up texture layout for small things with wide pitches (tiled)Eric Anholt2009-06-171-1/+1
* i965: Fall back or appropriately adjust offsets of drawing to tiled regions.Eric Anholt2009-06-173-3/+54
* Merge branch 'mesa_7_5_branch'Brian Paul2009-06-165-20/+54
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| * i965: fix bugs in projective texture coordinatesBrian Paul2009-06-165-20/+54
* | i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-161-0/+1
* | i965: interpolate colors with perspective correction by defaultBrian Paul2009-06-126-13/+38
* | intel: Add support for tiled textures.Eric Anholt2009-06-041-4/+5
* | i965: Support OPCODE_TRUNC in the brw_wm_fp.c code.Eric Anholt2009-06-023-1/+18
* | i965: fix whitespace in brw_tex_layout.cEric Anholt2009-05-211-32/+31
* | i956: Make state dependency of SF on drawbuffer bounds match Mesa's.Eric Anholt2009-05-211-2/+5
* | i965: rename var: s/tmp/vs_inputs/Brian Paul2009-05-211-8/+8
* | i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-05-141-8/+10
* | i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-05-144-13/+27
* | i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-05-141-0/+10
* | i965: enable additional code in emit_fb_write()Brian Paul2009-05-121-11/+10
* | i965: increase BRW_EU_MAX_INSNBrian Paul2009-05-121-1/+1
* | i965: commentBrian Paul2009-05-121-0/+4
* | i965: handle extended swizzle terms (0,1) in get_src_reg()Brian Paul2009-05-111-0/+8
* | i965: improve debug loggingRobert Ellison2009-05-081-0/+6
* | i965: fix segfault on low memory conditionsRobert Ellison2009-05-081-0/+7
* | intel: Add a metaops version of glGenerateMipmapEXT/SGIS_generate_mipmaps.Eric Anholt2009-05-082-0/+2
* | i965: const qualifiersBrian Paul2009-05-081-2/+2
* | i965: don't use GRF regs 126,127 for WM programsBrian Paul2009-05-082-5/+28
* | i965: relAddr local var (to make debug/test a little easier)Brian Paul2009-05-071-5/+6
* | i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt2009-05-061-13/+11
* | i965: Remove the forced lack of caching for renderbuffer surface state.Eric Anholt2009-05-061-11/+8
* | i965: Remove _NEW_PROGRAM from brw_wm_surfaces setup dependencies.Eric Anholt2009-05-061-2/+1
* | i965: Split WM constant buffer update from other WM surfaces.Eric Anholt2009-05-065-90/+95
* | i965: Disentangle VS constant surface state from WM surface state.Eric Anholt2009-05-067-186/+255
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