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path: root/src/mesa/drivers/dri/i965
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* i965: Add dumping of the sampler default color.Eric Anholt2010-11-181-0/+11
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* i965: Add state dumping for sampler state.Eric Anholt2010-11-181-2/+39
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* i965: Shut up spurious gcc warning about GLSL_TYPE enums.Eric Anholt2010-11-181-0/+4
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* glsl: Remove the ir_binop_cross opcode.Kenneth Graunke2010-11-172-29/+0
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* i965: Fix gl_FragCoord inversion when drawing to an FBO.Eric Anholt2010-11-143-3/+6
| | | | | | This showed up as cairo-gl gradients being inverted on everyone but Intel, where I'd apparently tweaked the transformation to work around the bug. Fixes piglit fbo-fragcoord.
* i965: Silence uninitialized variable warning.Vinson Lee2010-11-131-0/+1
| | | | | | Silences this GCC warning. brw_fs.cpp: In member function 'void fs_visitor::split_virtual_grfs()': brw_fs.cpp:2516: warning: unused variable 'reg'
* i965: re-enable gen6 IF statements in the fragment shader.Eric Anholt2010-11-102-6/+1
| | | | | | | | | | | | | | | | | | IF statements were getting flattened while they were broken. With Zhenyu's last fix for ENDIF's type, everything appears to have lined up to actually work. This regresses two tests: glsl1-! (not) operator (1, fail) glsl1-! (not) operator (1, pass) but fixes tests that couldn't work before because the IFs couldn't be flattened: glsl-fs-discard-01 occlusion-query-discard (and, naturally, this should be a performance improvement for apps that actually use IF statements to avoid executing a bunch of code).
* i965: Work around strangeness in swizzling/masking of gen6 math.Eric Anholt2010-11-101-11/+58
| | | | | | | | | | | | | | | | | | | | Sometimes we swizzled in a different channel it looked like, and sometimes we swizzled in zero. Or something. Having looked at the output of another code generator for this chip, this is approximately what they do, too: use align1 math on temporaries, and then move the results into place. Fixes: glean/vp1-EX2 test glean/vp1-EXP test glean/vp1-LG2 test glean/vp1-RCP test (reciprocal) glean/vp1-RSQ test 1 (reciprocal square root) shaders/glsl-cos shaders/glsl-sin shaders/glsl-vs-masked-cos shaders/vpfp-generic/vp-exp-alias
* Revert "i965: VS use SPF mode on sandybridge for now"Zhenyu Wang2010-11-102-5/+1
| | | | | | This reverts commit 9c39a9fcb2c76897e9b5aff68ce197a411c4e25c. Remove VS SPF mode, conditional instruction works for VS now.
* i965: fix dest type of 'endif' on sandybridgeZhenyu Wang2010-11-101-1/+1
| | | | That should also be immediate value for type W.
* i965: Add support for math on constants in gen6 brw_wm_glsl.c path.Eric Anholt2010-11-091-4/+5
| | | | Fixes 10 piglit cases that were assertion failing.
* i965: Allow OPCODE_SWZ to put immediates in the first arg.Eric Anholt2010-11-091-0/+1
| | | | | | | | | | | Fixes assertion failure with texture swizzling in the GLSL path when it's triggered (such as gen6 FF or ARB_fp shadow comparisons). Fixes: texdepth texSwizzle fp1-DST test fp1-LIT test 3
* i965: Silence uninitialized variable warning.Vinson Lee2010-11-041-1/+1
| | | | | | | Silences this GCC warning. brw_wm_fp.c: In function 'brw_wm_pass_fp': brw_wm_fp.c:966: warning: 'last_inst' may be used uninitialized in this function brw_wm_fp.c:966: note: 'last_inst' was declared here
* i965: Silence uninitialized variable warning.Vinson Lee2010-11-041-1/+1
| | | | | | Silences this GCC warning. brw_wm_fp.c: In function 'precalc_tex': brw_wm_fp.c:666: warning: 'tmpcoord.Index' may be used uninitialized in this function
* i965: Remove dead intel_structs.h file.Eric Anholt2010-11-031-132/+0
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* intel: Annotate debug printout checks with unlikely().Eric Anholt2010-11-0324-54/+49
| | | | | | | This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
* i965: refresh wm push constant also for BRW_NEW_FRAMENT_PROGRAM on gen6Zhenyu Wang2010-11-021-1/+1
| | | | | | Fix compiz crash. https://bugs.freedesktop.org/show_bug.cgi?id=31124
* i965: Update the gen6 stencil ref state when stencil state changes.Eric Anholt2010-10-281-1/+1
| | | | Fixes 6 piglit tests about stencil operations.
* i965: Upload required gen6 VS push constants even when using pull constants.Eric Anholt2010-10-281-8/+18
| | | | Matches pre-gen6, and fixes glsl-vs-large-uniform-array.
* i965: Update gen6 SF state when point state (sprite or attenuation) changes.Eric Anholt2010-10-281-0/+1
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* i965: Add user clip planes support to gen6.Eric Anholt2010-10-285-31/+123
| | | | | Fixes piglit user-clip, and compiz desktop switching when dragging a window and using just 2 desktops. Bug #30446.
* i965: Add bit operation support to the fragment shader backend.Kenneth Graunke2010-10-271-3/+12
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* i965: Make FS uniforms be the actual type of the uniform at upload time.Eric Anholt2010-10-276-9/+81
| | | | | | | | This fixes some insanity that would otherwise be required for GLSL 1.30 bit ops or gen6 integer uniform operations in general, at the cost of upload-time pain. Given that we only have that pain because mesa's mangling our integer uniforms to be floats, this something that should be fixed outside of the shader codegen.
* Track separate programs for each stageIan Romanick2010-10-272-5/+5
| | | | | The assumption is that all stages are the same program or that varyings are passed between stages using built-in varyings.
* i965: Disable register spilling on gen6 until it's fixed.Eric Anholt2010-10-261-1/+1
| | | | Avoids GPU hang on glsl-fs-convolution-1.
* i965: Fix VS URB entry sizing.Eric Anholt2010-10-261-1/+1
| | | | | | | | | I'm trying to clamp to a minimum of 1 URB row, not a maximum of 1. Fixes: glsl-kwin-blur glsl-max-varying glsl-routing
* i965: Drop the eot argument to read messages, which can never be set.Eric Anholt2010-10-261-24/+19
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* i965: Add support for constant buffer loads on gen6.Eric Anholt2010-10-261-2/+26
| | | | Fixes glsl-fs-uniform-array-5.
* i965: Set up the constant buffer on gen6 when it's needed.Eric Anholt2010-10-261-0/+1
| | | | | This was slightly confused because gen6_wm_constants does the push constant buffer, while brw_wm_constants does pull constants.
* i965: Fix typo in comment about state flags.Eric Anholt2010-10-261-1/+1
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* i965: Handle new ir_unop_round_even in channel expression splitting.Eric Anholt2010-10-261-0/+1
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* i965: Add support for discard instructions on gen6.Eric Anholt2010-10-261-10/+41
| | | | | | It's a little more painful than before because we don't have the handy mask register any more, and have to make do with cooking up a value out of the flag register.
* i965: Add disasm for the flag register.Eric Anholt2010-10-261-0/+3
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* i965: Clear some undefined fields of g0 when using them for gen6 FB writes.Eric Anholt2010-10-261-0/+14
| | | | | This doesn't appear to help any testcases I'm looking at, but it looks like it's required.
* i965: Use SENDC on the first render target write on gen6.Eric Anholt2010-10-263-4/+13
| | | | | | This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color.
* i965: Clarify an XXX comment in FB writes with real info.Eric Anholt2010-10-261-1/+2
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* i965: Add EU code for dword scattered reads (constant buffer array indexing).Eric Anholt2010-10-262-0/+45
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* i965: Add support for pull constants to the new FS backend.Eric Anholt2010-10-2210-105/+213
| | | | Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
* i965: Move the FS disasm/annotation printout to codegen time.Eric Anholt2010-10-222-54/+35
| | | | | | This makes it a lot easier to track down where we failed when some code emit triggers an assert. Plus, less memory allocation for codegen.
* i965: Be more aggressive in tracking live/dead intervals within loops.Eric Anholt2010-10-211-13/+41
| | | | | | Fixes glsl-fs-convolution-2, which was blowing up due to the array access insanity getting at the uniform values within the loop. Each temporary was considered live across the whole loop.
* i965: Correct scratch space allocation.Eric Anholt2010-10-213-12/+15
| | | | | | | | | | One, it was allocating increments of 1kb, but per thread scratch space is a power of two. Two, the new FS wasn't getting total_scratch set at all, so everyone thought they had 1kb and writes beyond 1kb would go stomping on a neighbor thread. With this plus the previous register spilling for the new FS, glsl-fs-convolution-1 passes.
* i965: Don't emit register spill offsets directly into g0.Eric Anholt2010-10-211-6/+22
| | | | | | | g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
* i965: Add support for register spilling.Eric Anholt2010-10-216-55/+315
| | | | | It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
* i965: Fix gl_FrontFacing emit on pre-gen6.Eric Anholt2010-10-211-1/+0
| | | | | | | | | It's amazing this code worked. Basically, we would get lucky in register allocation and the tests using frontfacing would happen to allocate gl_FrontFacing storage and the instructions generating gl_FrontFacing but pointing at another register to the same hardware register. Noticed during register spilling debug, when suddenly they didn't get allocatd the same storage.
* i965: Split register allocation out of the ever-growing brw_fs.cpp.Eric Anholt2010-10-213-216/+266
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* i965: Use the new style of IF statement with embedded comparison on gen6.Eric Anholt2010-10-192-4/+113
| | | | | "Everyone else" does it this way, so follow suit. It's fewer instructions, anyway.
* i965: Set the source operand types for gen6 if/else/endif to integer.Eric Anholt2010-10-191-6/+6
| | | | | I don't think this should matter, but I'm not sure, and it's recommended by a kernel checker in fulsim.
* i965: Add EU emit support for gen6's new IF instruction with comparison.Eric Anholt2010-10-192-1/+31
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* i965: Disable thread dispatch when the FS doesn't do any work.Eric Anholt2010-10-193-4/+49
| | | | | | This should reduce the cost of generating shadow maps, for example. No performance difference measured in nexuiz, though it does trigger this path.
* i965: Remove the gen6 emit_mi_flushes I sprinkled around the driver.Eric Anholt2010-10-1910-26/+0
| | | | | These were for debugging in bringup. Now that relatively complicated apps are working, they haven't helped debug anything in quite a while.
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