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* i965/miptree: avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho2018-07-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | GCC 8.1.1 is having a hard time identifying that the values are properly initialized when used. In the 'memset_value' case, we pass the uninitialized value to another function (that will use only if the conditions match the initialization). Just give enough hint to the compiler to figure things out. Fixes the warnings ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function ‘intel_miptree_alloc_aux’: ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1839:18: warning: ‘memset_value’ may be used uninitialized in this function [-Wmaybe-uninitialized] mt->aux_buf = intel_alloc_aux_buffer(brw, &aux_surf, needs_memset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ memset_value); ~~~~~~~~~~~~~ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1698:10: warning: ‘initial_state’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (wants_memset) ^ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1772:23: note: ‘initial_state’ was declared here enum isl_aux_state initial_state; ^~~~~~~~~~~~~ Reviewed-by: Anuj Phogat <[email protected]>
* i965: batchbuffer: write correct canonical offset with softpinLionel Landwerlin2018-07-181-1/+2
| | | | | | | | | | | | | Addresses in the command streams should be in canonical form (i.e bit[63:48] == bit[47]). If the [bo->gtt_offset, bo->gtt_offset + target_offset] range contains the address 0x800000000000, the current code will fail that criteria. v2: Fix missing include (Lionel) Fixes: 1c9053d0765dc6 ("i965: Prepare batchbuffer module for softpin support.") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-6/+6
| | | | | | | | | | | | | | SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Allocate MS texture BOs as BUSYNanley Chery2018-07-131-2/+2
| | | | | | These buffer objects are never accessed with the CPU. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Inline make_separate_stencilNanley Chery2018-07-131-23/+6
| | | | | | | | | | Note that the separate stencil miptree now has the same alloc_flag as the depth component. Only stencil renderbuffers (as opposed to textures) have BO_ALLOC_BUSY. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Init r8stencil_needs_update to falseNanley Chery2018-07-131-3/+4
| | | | | | | | | | | | | | | The current behavior masked two bugs where the flag was not set to true after modifying the stencil texture. One case was a regression introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd and another was a bug in the depthstencil mapping code. These have since been fixed. To prevent such bugs from being masked in the future, initialize r8stencil_needs_update to false. v2: Keep the delayed allocation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Refactor miptree_createNanley Chery2018-07-131-36/+12
| | | | | | | | Enable a future patch to create the r8stencil_mt in this function. v2: Explicitly set etc_format to MESA_FORMAT_NONE (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add and use mt_surf_usageNanley Chery2018-07-131-13/+25
| | | | | | v2: Make mt_fmt const (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share alloc_flags in miptree_createNanley Chery2018-07-131-7/+4
| | | | | | | | | Note that this maintains BO_ALLOC_BUSY for depth renderbuffers, but not depth textures. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share the miptree format in miptree_createNanley Chery2018-07-131-15/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share tiling_flags in miptree_createNanley Chery2018-07-131-8/+7
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Delete MIPTREE_CREATE_LINEARNanley Chery2018-07-132-13/+3
| | | | | | | | | This enum constant was introduced to enable blit maps with intel_miptree_create da2880bea05bfc87109477ab026a7f5401fc8f0c. Now that such maps use the more direct make_surface function which allows you to specify the tiling directly, the constant is no longer being used. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use make_surface in map_blitNanley Chery2018-07-131-6/+6
| | | | | | | Do this so that we don't have to special case linearly-tiled depth buffers in miptree_create. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/draw: Fix adding the stencil bo to the depth cacheNanley Chery2018-07-131-1/+1
| | | | | | | | | Fix the case where stencil writes are enabled on a depth stencil texture. Found by inspection. v2: Fix message to allow for depth stencil writes (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/draw: Set the r8stencil flag after drawingNanley Chery2018-07-131-1/+11
| | | | | | | | | | | | | | Fixes the regresion introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd "i965: Use ISL for emitting depth/stencil/hiz state on gen6+" Found by inspection. Prevents regressing the piglit test, fbo-depth-array stencil-draw, later on in this series. Cc: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Set the r8stencil flag in map_depthstencilNanley Chery2018-07-131-1/+3
| | | | | | | | | | | Found by initializing the r8stencil_needs_update to false in make_separate_stencil_surface. Prevents regressing the piglit test arb_stencil_texturing-draw, later on in the series. Cc: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Set the r8stencil flag in miptree_finish_writeNanley Chery2018-07-134-17/+4
| | | | | | This seems to be the most appropriate place. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use the correct BLT pitchNanley Chery2018-07-121-6/+6
| | | | | | | | | | Retile miptrees to a linear tiling less often. Retiling can cause issues with imported BOs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738 Suggested-by: Chris Wilson <[email protected]> Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965/miptree: Drop an if case from retile_as_linearNanley Chery2018-07-121-4/+0
| | | | | | | | | | | Drop an if statement whose predicate never evaluates to true. row_pitch belongs to a surface with non-linear tiling. According to isl_calc_tiled_min_row_pitch, the pitch is a multiple of the tile width. By looking at isl_tiling_get_info, we see that non-linear tilings have widths greater than or equal to 128B. Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: Make blt_pitch publicNanley Chery2018-07-122-10/+12
| | | | | | | We'd like to reuse this helper. Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: fix typo (wrong gen number) in commentCaio Marcelo de Oliveira Filho2018-07-121-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Support saving the gen program with glGetProgramBinaryJordan Justen2018-07-091-6/+66
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add flag_state param to brw_search_cacheJordan Justen2018-07-0912-45/+35
| | | | | | | | | | This allows brw_search_cache to be used to find programs without causing extra state to be emitted in the case where the program isn't being made active. (For example, to find the program to save out with the ARB_get_program_binary interface.) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: Add gl_shader_program param to ProgramBinarySerializeDriverBlobJordan Justen2018-07-093-1/+12
| | | | | | | | | | This might be required because some stages might generate different programs depending on the other stages in the program. For example, the i965 driver's tessellation control stage depends on the tessellation evaluation shader. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_populate_default_keyJordan Justen2018-07-0912-73/+195
| | | | | | | | | We will need to populate the default key for ARB_get_program_binary to allow us to retrieve the default gen program to store in the program binary. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Replace brw_setup_tex_for_precompile brw with devinfoJordan Justen2018-07-098-9/+8
| | | | | | | | Trying to make sure the setup of the default program key is not dependent on the GL state. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Regenerate blob without gen program for shader cacheJordan Justen2018-07-091-1/+63
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add support for driver cache blob containing the gen programJordan Justen2018-07-091-0/+41
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Use brw_prog_key_set_id in disk cache load/store codeJordan Justen2018-07-091-16/+8
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_prog_key_set_id helper to set the program id on any stageJordan Justen2018-07-092-0/+19
| | | | | | | | | | | For saving programs (shader cache; get program binary) it is useful to set the id to 0, with the stage being a parameter. For restoring programs it is useful to set the id to the id allocated to the program at creation time. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_stage_cache_id to map gl stages to brw cache_idsJordan Justen2018-07-092-0/+17
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_(read|write)_blob_program_data functionsJordan Justen2018-07-093-41/+61
| | | | | | | | We will want to use these for both the disk shader cache, and for the ARB_get_program_binary. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_program_deserialize_driver_blobJordan Justen2018-07-093-21/+48
| | | | | | | | | | | brw_program_deserialize_driver_blob will be a more generic form of brw_program_deserialize_nir. In addition to nir, it will also be able to extract gen binaries and upload them to the program cache. In this commit, it continues to only support nir. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Move brw_program_*serialize_nir to brw_program_binary.cJordan Justen2018-07-092-37/+37
| | | | | | | | This will allow get_program_binary to add the gen program into its serialization in addition to just the nir program. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Use ShaderCacheSerializeDriverBlob driver functionJordan Justen2018-07-093-11/+7
| | | | | | | | This function is called just before the gl_program::driver_cache_blob is saved out as part of the gl_program serialization. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965/icl: Don't set float blend optimization bit in CACHE_MODE_SSAnuj Phogat2018-07-091-4/+0
| | | | | | | | | | | | CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: fix clear color bo address relocationLionel Landwerlin2018-07-071-1/+1
| | | | | | Fixes: 7987d041fda0c9 ("i965/surface_state: Emit the clear color address instead of value.") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the new nir atomic counter linker for SPIR-V shadersNeil Roberts2018-07-031-0/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* i965: enable AtomicStorage capability for gen7+Alejandro Piñeiro2018-07-031-0/+1
| | | | | | That is the same gen requirement for ARB_shader_atomic_counters. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Fix BRW_NEW_NUM_SAMPLES to be in .brw, not .mesaKenneth Graunke2018-07-021-2/+2
| | | | | | | | This is the wrong kind of dirty bit. Caught by GCC warnings, due to 64-bit values being truncated to 32 bits. Fixes: b95b0e2918c052068caeb4f6c2802ba89be043a3 (intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaround) Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa/i965: Allow decompressing ETC2 to GL_RGBATomeu Vizoso2018-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | When Mesa itself implements ETC2 decompression, it currently decompresses to formats in the GL_BGRA component order. That can be problematic for drivers which cannot upload the texture data as GL_BGRA, such as Virgl when it's backed by GLES on the host. So this commit adds a flag to _mesa_unpack_etc2_format so callers can specify the optimal component order. In Gallium's case, it will be requested if the format isn't in PIPE_FORMAT_B8G8R8A8_SRGB format. For i965, it will remain GL_BGRA, as before. v2: * Remove unnecesary include (Emil Velikov) Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaroundJason Ekstrand2018-06-281-0/+17
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Add fields to wm_prog_data for SIMD32 dispatchJason Ekstrand2018-06-282-0/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Add plumbing for shader time in 32-wide FS dispatch mode.Francisco Jerez2018-06-283-2/+11
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/compiler: Add and use helpers for working with KSP indicesJason Ekstrand2018-06-282-23/+47
| | | | | | | | The pixel shader dispatch table is kind-of a confusing mess. This adds some helpers for dealing with it and for easily extracting the correct data from wm_prog_data. Reviewed-by: Matt Turner <[email protected]>
* i965: Re-arrange shader kernel setup in WM stateJason Ekstrand2018-06-281-37/+57
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/bufmgr: Use the correct argument order for bo_alloc_internalJason Ekstrand2018-06-271-2/+2
| | | | | | | The memzone and flags parameters were accidentally flipped in the call from brw_bo_alloc_tiled_2d. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: small cleanup in blorp debug printing output (trivial)Tapani Pälli2018-06-271-1/+1
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir: Remove old-school deref chain supportJason Ekstrand2018-06-221-1/+0
| | | | | | | Acked-by: Rob Clark <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Use derefs in nir_lower_samplersJason Ekstrand2018-06-221-2/+0
| | | | | | | | | | | We change glsl_to_nir to provide derefs for bot textures and samplers while we're at it. This makes the lowering much easier since we only either replace sources or remove them. Acked-by: Rob Clark <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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