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* i965: Add texrect scale parameters before pointers to ParameterValues.Eric Anholt2012-12-283-0/+24
| | | | | | | | | | | | | If adding scale parameters during program compile caused a realloc of ParameterValues, then the driver uniform storage set up by _mesa_associate_uniform_storage() would point to potentially freed memory. Note that this uses TexturesUsed, which may change at runtime for GLSL when sampler uniforms change. This is a flaw in our handling of texrect in general, and not one I'm fixing currently. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix a typo in a comment.Eric Anholt2012-12-281-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add a note about a bug from the no-recompile-on-sampler-updates change.Eric Anholt2012-12-281-0/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix border color handling for deprecated SNORM formats.Eric Anholt2012-12-261-2/+29
| | | | | | | | | | We don't have native hardware support for these, so they get promoted to RGBA, in which case we don't have hardware dealing with the channel swizzling for us. Fixes piglit EXT_texture_snorm/texwrap formats bordercolor (-swizzled). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Start using HIZ for Z16 textures.Eric Anholt2012-12-261-0/+1
| | | | | | | | | | I had left this out for a long time because it regressed some depthstencil-render-miplevels cases when it was enabled. Now that the bugs causing those are fixed, there's nothing stopping us. Improves glbenchmark 2.1 offscreen performance by 7.3% +/- 2.8% (n=10). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add perf debug for depth/stencil alignment workaround.Eric Anholt2012-12-221-0/+16
| | | | | | | | Fixing these rendering bugs has been implicated in performance regressions (which may be unfixable), but at least knowing that it's happening should help diagnose those regressions. Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix hiz resolves getting stomped by depth offset validation.Eric Anholt2012-12-221-5/+5
| | | | | | | Fixes all the remaining non-Z32F_S8 depthstencil-render-miplevels tests in piglit. Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix gl_VertexID when there are no other vertex inputs.Paul Berry2012-12-181-3/+3
| | | | | | | | | | | | brw_emit_vertices contains special case logic to handle the case where a vertex shader doesn't read any inputs. This special case logic was incorrectly activating in the case were the only vertex input is gl_VertexID. As a result, if a shader used gl_VertexID but used no other inputs, then all vertices got a gl_VertexID of zero. Fixes oglconform test "ubo-usage advanced.transform_feedback". Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make a function is_transform_feedback_active_and_unpaused.Paul Berry2012-12-184-8/+7
| | | | | | | | | | The rather unweildy logic for determining this condition was repeated in a large number of places. This patch consolidates it to a single inline function. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: refactor _mesa_compute_max_transform_feedback_vertices from i965.Paul Berry2012-12-181-12/+4
| | | | | | | | | | | | | | | | | Previously, the i965 driver contained code to compute the maximum number of vertices that could be written without overflowing any transform feedback buffers. This code wasn't driver-specific, and for GLES3 support we're going to need to use it in core mesa. So this patch moves the code into a core mesa function, _mesa_compute_max_transform_feedback_vertices(). Reviewed-by: Ian Romanick <[email protected]> v2: Eliminate C++-style variable declarations, since these won't work with MSVC. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Change args to vbo_count_tessellated_primitives.Paul Berry2012-12-181-1/+3
| | | | | | | | | | | | | | No functional change--this simply paves the way to allow futures patches to call vbo_count_tessellated_primitives() during error checking, before the _mesa_prim struct has been constructed. This will be needed for GLES3, which requires draw calls to fail if there is not enough space available in transform feedback buffers to accommodate the primitives to be drawn. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* drivers: compute version and then initialize exec tableJordan Justen2012-12-161-0/+8
| | | | | | | | This change forces the context version to be computed before initilizing the exec dispatch tables. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move BRW_MAX_GRF and similar defines to brw_reg.h.Kenneth Graunke2012-12-152-18/+17
| | | | | | These don't really belong in brw_structs.h. Reviewed-by: Eric Anholt <[email protected]>
* i965: Split struct brw_reg out from brw_eu.h into its own header.Kenneth Graunke2012-12-152-709/+778
| | | | | | | | | | | | | | | | | | | struct brw_instruction and the related instruction emitting code won't be useful on Gen8+, as the instruction encoding changed. However, the struct brw_reg code is still extremely valuable. While we're at it, fix up some style points: - s/GLuint/unsigned/g - s/GLint/int/g - s/GLshort/int16_t/g - s/GLushort/uint16_t/g - s/INLINE/inline/g - Replace tabs with spaces - Put return types on a separate line from the function name/parameters - Remove trailing whitespace - Remove extraneous whitespace around function parameters Reviewed-by: Eric Anholt <[email protected]>
* i965: Add missing autoconf bits so test_vec4_register_coalesce will buildIan Romanick2012-12-141-0/+3
| | | | | Signed-off-by: Ian Romanick <[email protected]> Tested-by: Eric Anholt <[email protected]>
* i965: Generalize VS compute-to-MRF for compute-to-another-GRF, too.Eric Anholt2012-12-143-61/+128
| | | | | | | | | No statistically significant performance difference on glbenchmark 2.7 (n=60). It reduces cycles spent in the vertex shader by 3.3% +/- 0.8% (n=5), but that's only about .3% of all cycles spent according to the fixed shader_time. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Extend opt_compute_to_mrf to handle limited "reswizzling"Eric Anholt2012-12-143-9/+113
| | | | | | | | | | | | | The way our visitor works, scalar expression/swizzle results that get stored in channels other than .x will have an intermediate MOV from their result in the .x channel to the real .y (or whatever) channel, and similarly for vec2/vec3 results. By knowing how to adjust DP4-type instructions for optimizing out a swizzled MOV, we can reduce instructions in common matrix multiplication cases. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add a unit test for opt_compute_to_mrf().Eric Anholt2012-12-143-2/+133
| | | | | | | | | | | | | The compute-to-mrf code is really twitchy, and it's hard to construct GLSL testcases for it. This unit test is also really hard to work with (for example, if your instruction is removed by dead code elimination, you end up inspecting something irrelevant), but I did use it for debugging some of the commits to follow. I called it test_vec4_register_coalesce because the compute-to-mrf code is about to morph into that. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Drop an unnecessary _safe on a list walk.Eric Anholt2012-12-141-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add a note explaining a detail of register_coalesce_2().Eric Anholt2012-12-141-0/+21
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Also consider HALTs a potential block end.Eric Anholt2012-12-141-0/+1
| | | | | | | | The final halt of the fragment shader turns off the remaining channels, then jumps such that everything is turned back on. So, we can have our last ENDIF of the shader point at that directly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Jump to the end of the next outer conditional block on ENDIFs.Kenneth Graunke2012-12-141-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the Ivybridge PRM, Volume 4, Part 3, section 6.24 (page 172): "The endif instruction is also used to hop out of nested conditionals by jumping to the end of the next outer conditional block when all channels are disabled." Also: "Pseudocode: Evaluate(WrEn); if ( WrEn == 0 ) { // all channels false Jump(IP + JIP); }" First, ENDIF re-enables any channels that were disabled because they didn't match the conditional. If any channels are active, it proceeds to the next instruction (IP + 16). However, if they're all disabled, there's no point in walking through all of the instructions that have no effect---it can jump to the next instruction that might re-enable some channels (an ELSE, ENDIF, or WHILE). Previously, we always set JIP on ENDIF instructions to 2 (which is measured in 8-byte units). This made it do Jump(IP + 16), which just meant it would go to the next instruction even if all channels were off. It turns out that walking over instructions while all the channels are disabled like this is worse than just instruction dispatch overhead: if there are texturing messages, it still costs a couple hundred cycles to not-actually-read from the texture results. This patch finds the next instruction that could re-enable channels and sets JIP accordingly. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Fix setup for textureGrad(samplerCubeArray, coord, dPdx, dPdy)Eric Anholt2012-12-141-7/+12
| | | | | | Caught by tex_grad-01.frag. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Move the failure for gen7 16-wide intdiv to emit_math().Eric Anholt2012-12-142-7/+4
| | | | | | | The cube map array code adds another caller of emit_math(), which needs this check. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fs: Add fixup for textureSize on Gen6/7Chris Forbes2012-12-141-0/+11
| | | | | | | | | | | | | | | V2: Moved up into emit(ir_texture *) to avoid duplication and fix ordering for Gen7; Gen6 math quirks moved into previous patches. Tested on Gen6 only; passes all the cube_map_array piglits. V3: Fixed weird whitespace V4: Use sampler->type; otherwise broken on arrays of samplers. v5: Minor style fixes (by anholt) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fs: fix gen6+ math operands in one placeChris Forbes2012-12-142-28/+33
| | | | | | | | | | V4: Fix various style nits as pointed out by Eric, and expand IMM operands on both Gen6 and Gen7. v5: minor style nits (by anholt) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: vs: Add fixup for textureSize with cube array samplersChris Forbes2012-12-141-0/+13
| | | | | | | | | | | V3: Fixed weird whitespace V4: Use sampler's type rather than variable's type; otherwise broken with arrays of samplers. (Thanks Eric) v5: Fix a couple more style nits (by anholt) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix gen6+ math operand quirks in one placeChris Forbes2012-12-142-34/+28
| | | | | | | | | | | This causes immediate values to get moved to a temp on gen7, which is needed for an upcoming change but hadn't happened in the visitor until then. v2: Drop gen > 7 checks (doesn't exist), and style-fix comments (changes by anholt). Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add various plumbing for cubemap arraysChris Forbes2012-12-145-3/+11
| | | | | | | | V4: Fixed style nits Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add empirically-determined instruction latencies for gen7.Eric Anholt2012-12-141-3/+179
| | | | | | | | | | | | | | | | v2: Actually switch on the other math instructions mentioned in the comment. v3: Add timing data for textureSize(), and clean up some long comment lines. Testing shader_time of fs16 shaders on a few frames of various apps: nexuiz improved by 2.9% +/- 1.5% (n=10) no difference on GLB2.5 (n=36, outliers removed) no difference on GLB2.7 (n=25) etqw improved by 2.6% +/- 2.2% (n=25) no difference on lightsmark (n=25) Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix the clock increment in scheduling.Eric Anholt2012-12-141-3/+15
| | | | | | | I've tested this to be true with various ALU ops on gen7 (with the exception of MADs, which go at either 3 or 4 cycles per dispatch). Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Move the old gen4 bspec-based scheduling info to a helper func.Eric Anholt2012-12-141-33/+41
| | | | | | For gen7 everything changes, and we have actual information on latency. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Set up gen7 UBO loads as sends from GRFs.Eric Anholt2012-12-145-7/+114
| | | | | | | | | | | | This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Before reg alloc, schedule instructions to reduce live ranges.Eric Anholt2012-12-141-6/+41
| | | | | | | | | | | | | | | | | | | | | | | | | This came from an idea by Ben Segovia. 16-wide pixel shaders are very important for latency hiding on i965, so we want to try really hard to get them. If scheduling an instruction makes some set of instructions available, those are probably the ones that make the instruction's result dead. By choosing those first, we'll have a tendency to reduce the amount of live data as opposed to creating more. Previously, we were sometimes getting this behavior out of the scheduler, which was what produced the scheduler's original performance wins on lightsmark. Unfortunately, that was mostly an accident of the lame instruction latency information that I had, which made it impossible to fix the actual scheduling for performance. Now that we've fixed the scheduling for setup for register allocation, we can safely update the latency parameters for the final schedule. In shader-db, we lose 37 16-wide shaders, but gain 90 new ones. 4 shaders that were spilling change how many registers spill, for a reduction of 70/3899 instructions. v2: Simplify the new loop. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Add some optional debug printfs to scheduling.Eric Anholt2012-12-141-0/+21
| | | | | | Seeing when instructions become available to schedule is really useful. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Schedule instructions both before and after register allocation.Eric Anholt2012-12-143-18/+78
| | | | Acked-by: Kenneth Graunke <[email protected]>
* i965: Make sure that the shader_time report at context destroy happens.Eric Anholt2012-12-141-0/+3
| | | | | | Otherwise, you end up with some report from within a second of context destroy, which is now what you really want for testing the impact of changes
* i965: Print a total time for the different shader stages.Eric Anholt2012-12-141-10/+38
| | | | | | | | | Sometimes I've got a patch for a performance optimization that's not showing a statistically significant performance difference on reported FPS, but still seems like a good idea because it ought to reduce time spent in the shader. If I can see the total number of cycles spent in the shader stage being optimized, it may show that the patch is still worthwhile (or point out that it's actually broken in some way).
* i965: Scale shader_time to compensate for resets.Eric Anholt2012-12-144-9/+83
| | | | | | | | | | Some shaders experience resets more than others, which skews the numbers reported. Attempt to correct for this by linearly scaling according to the number of resets that happen. Note that will not be accurate if invocations of shaders have varying times and longer invocations are more likely to reset. However, this should at least be better than the previous situation.
* i965: Adjust the split between shader_time_end() and shader_time_write().Eric Anholt2012-12-144-51/+55
| | | | | | I'm about to emit other kinds of writes besides time deltas, and it turns out with the frequency of resets, we couldn't really use the old time delta write() function more than once in a shader.
* i965: Fix disassembly of jump targets on Gen7.Kenneth Graunke2012-12-121-4/+9
| | | | | | Gen7 stores the JIP/UIP bits in different places. Reviewed-by: Eric Anholt <[email protected]>
* i965: Make try_rewrite_rhs_to_dst compare VGRF size to regs written.Kenneth Graunke2012-12-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | try_rewrite_rhs_to_dst is a quick optimization to avoid generating new temporaries (and MOVs from those temporaries to the dest) for every expression tree we visit. By generating better code in simple cases, we reduce the burden on later optimization passes like register coalescing. Previously, we compared inst->regs_written() to lhs->vector_elements to make sure the instruction generating our value wrote the same number of components as our destination register. However, this fails in some cases. One example is texturing (which produces a vec4) into gl_FragData[i]. Technically, gl_FragData[i] is also a vec4. However, the destination VGRF actually has size 4n (where n is the size of the array). split_virtual_grfs() can't split VGRFs that are used by SEND messages which require contiguous destination registers (like texturing), and register allocation needs all VGRFs to have sizes between 1 and 4. Amnesia: The Dark Descent hits this case: a texturing instruction (4 components) gets rewritten to the gl_FragData output register (which was 4*3 = 12 components), causing the register allocator to hit the "we rely on split_virtual_grfs" assertion. This makes it possible to play Amnesia. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Improve performance of shaders that start out with a discard.Eric Anholt2012-12-116-7/+148
| | | | | | | | | | | | | | I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Rewrite discards to use a flag subreg to track discarded pixels.Eric Anholt2012-12-118-73/+46
| | | | | | | | | This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add an instruction flag for choosing the flag subregister.Eric Anholt2012-12-116-13/+42
| | | | | | | | We're going to redo discard handling to track discards in the other flag subregister, saving instructions in the discard and allowing predicated jumps out to the end of the shader. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Let brw_flag_reg() choose the flag reg and subreg.Eric Anholt2012-12-114-7/+7
| | | | | | We're about to start using the f0.1 subregister. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Print the flag reg updated by conditional modifiers.Eric Anholt2012-12-111-1/+15
| | | | | | | This makes our output more consistent with other disasm tools, and will be necessary when we start using f0.1. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add the new flag_reg_nr instruction field from IVB.Eric Anholt2012-12-112-5/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Correct the name and usage of the flag subregister number field.Eric Anholt2012-12-114-15/+15
| | | | | | | We've been calling it a register number, it's actually the subregister, and things will get confusing once we start using it if it isn't fixed. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove bogus flag_reg_nr field from bits3.Eric Anholt2012-12-111-4/+2
| | | | | | | There's a flag subreg nr field in bits2 next to src0.vertstride, but there shouldn't be anything in bits3 next to src1.vertstride. Reviewed-by: Kenneth Graunke <[email protected]>
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