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* i965: drop unused assignmentEric Engestrom2018-08-161-2/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: do not emit empty surface stateErik Faye-Lund2018-08-151-0/+5
| | | | | | | | | | | | | | If called with an empty size, brw_emit_buffer_surface_state asserts. We already have a dedicated helper for uploading nothing, so let's use that instead. Avoids an assert in dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_vertex when running a debug build of i965. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/ppgtt: 4096 replaced by PAGE_SIZESergii Romantsov2018-08-151-6/+6
| | | | | | | Usage of number 4096 replaced by PAGE_SIZE. Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/ppgtt: memory address alignmentSergii Romantsov2018-08-151-4/+3
| | | | | | | | | | | | | | | | | | Kernel (for ppgtt) requires memory address to be aligned to page size (4096). -v2: added marking that also fixes initial commit 01058a552294. -v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned instead of alignment of offsets (Chris Wilson). -v4: changes related to PAGE_SIZE moved to separate commit -v5: restored alignment to page-size for 0-size. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997 Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.) Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to brw_bufmgr.) Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Emitting 3DSTATE_SO_BUFFER of 0-size.Sergii Romantsov2018-08-151-4/+5
| | | | | | | Avoided filling of whole structure and bo-allocation if size of surface is 0. Signed-off-by: Sergii Romantsov <[email protected]>
* i965/nir: Use the nir copy of shader_info to handle gl_PatchVerticesInNeil Roberts2018-08-131-1/+1
| | | | | | | | | | | | | | | | | | Instead of using the copy of shader_info stored in gl_program, it now uses the one in nir_shader. This is needed for SPIR-V because the info.tess.tcs_vertices_out is filled in via _mesa_spirv_to_nir which happens much later than with a GLSL shader. The copy of shader_data in gl_program is only updated later via brw_shader_gather_info but that is too late. For GLSL this shouldn't create any problems because the nir copy of the shader_info is immediately copied from the gl_program in glsl_to_nir. v2: updated after commit "i965: Combine both gl_PatchVerticesIn lowering passes." (488972) (Alejandro Piñeiro) Reviewed-by: Timothy Arceri <[email protected]>
* i965: enable EXT_render_snormTapani Pälli2018-08-131-0/+1
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel: Switch the order of the 2x MSAA sample positionsJason Ekstrand2018-08-112-9/+9
| | | | | | | | The Vulkan 1.1.82 spec flipped the order to better match D3D. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* meson: Build with Python 3Mathieu Bridon2018-08-101-1/+1
| | | | | | | | | | | | Now that all the build scripts are compatible with both Python 2 and 3, we can flip the switch and tell Meson to use the latter. Since Meson already depends on Python 3 anyway, this means we don't need two different Python stacks to build Mesa. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* i965: Only enable depth IZ signals if there's an actual depthbuffer.Kenneth Graunke2018-08-091-3/+8
| | | | | | | | | | | | | According to the G45 PRM Volume 2 Page 265 we're supposed to only set these signals when there is an actual depth buffer. Note that we already do this for the stencil buffer by virtue of brw->stencil_enabled invoking _mesa_is_stencil_enabled(ctx) which checks whether the current drawbuffer's visual has stencil bits (which is updated based on what buffers are bound). We just need to do it for depth as well. Not observed to fix anything. Reviewed-by: Jason Ekstrand <[email protected]>
* dri: Add param driCreateConfigs(mutable_render_buffer)Chad Versace2018-08-071-3/+3
| | | | | | | | | If set, then the config will have __DRI_ATTRIB_MUTABLE_RENDER_BUFFER, which translates to EGL_MUTABLE_RENDER_BUFFER_BIT_KHR. Not used yet. Reviewed-by: Tapani Pälli <[email protected]>
* i965: gen_shader_sha1() doesn't use the brw_contextEric Engestrom2018-08-071-4/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: add gl_renderbuffer::NumStorageSamplesMarek Olšák2018-08-041-0/+2
| | | | Reviewed-by: Brian Paul <[email protected]>
* intel/compiler: Add brw_get_compiler_config_value for disk cacheJordan Justen2018-08-011-1/+2
| | | | | | | | | | | | | | | | | | | During code review, Jason pointed out that: 2b3064c0731 "i965, anv: Use INTEL_DEBUG for disk_cache driver flags" Didn't account for INTEL_SCALER_* environment variables. To fix this, let the compiler return the disk_cache driver flags. Another possible fix would be to pull the INTEL_SCALER_* into INTEL_DEBUG bits, but as we are currently using 41 of 64 bits, I didn't think it was a good use of 4 more of these bits. (5 since INTEL_PRECISE_TRIG needs to be accounted for as well.) Cc: Jason Ekstrand <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disable shader cache with INTEL_DEBUG=shader_timeJordan Justen2018-08-011-0/+3
| | | | | | | | | | | | | | | | | | | Shader time hard codes an index of the shader time buffer within the gen program. In order to support shader time in the disk shader cache, we'd need to add the shader time index into the program key. This should work, but probably is not worth it for this particular debug feature. Therefore, let's just disable the disk shader cache if the shader time debug feature is used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106382 Fixes: 96fe36f7acc "i965: Enable disk shader cache by default" Cc: Eero Tamminen <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: enable XFB and GeometryStreams for gen7+Alejandro Piñeiro2018-07-311-0/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* i965: Link XFB varyings for SPIR-V shadersNeil Roberts2018-07-311-0/+1
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* i965: implement GL_MESA_framebuffer_flip_y [v3]Fritz Koenig2018-07-279-45/+43
| | | | | | | | | | | | | | Instead of using _mesa_is_winsys_fbo or _mesa_is_user_fbo to infer if an fbo is flipped use the FlipY flag. v2: * additional window-system framebuffer checks [for jason] v3: * s/inverted_y/flip_y/g [for chadv] * s/InvertedY/FlipY/g [for chadv] Reviewed-by: Chad Versace <[email protected]>
* mesa: GL_MESA_framebuffer_flip_y extension [v4]Fritz Koenig2018-07-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Adds an extension to glFramebufferParameteri that will specify if the framebuffer is vertically flipped. Historically system framebuffers are vertically flipped and user framebuffers are not. Checking to see the state was done by looking at the name field. This adds an explicit field. v2: * updated spec language [for chadv] * correctly specifying ES 3.1 [for chadv] * refactor access to rb->Name [for jason] * handle GetFramebufferParameteriv [for chadv] v3: * correct _mesa_GetMultisamplefv [for kusmabite] v4: * update spec language [for chadv] * s/GLboolean/bool/g [for chadv] * s/InvertedY/FlipY/g [for chadv] * s/inverted_y/flip_y/g [for chadv] * assert changes [for chadv] Reviewed-by: Chad Versace <[email protected]>
* i965/icl: Disable binding table prefetchingTopi Pohjolainen2018-07-271-1/+13
| | | | | | | | | | | | | Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to disable prefetching of binding tables for ICLLP A0 and B0 steppings. It fixes multiple gpu hangs in ext_framebuffer_multisample* tests on ICLLP B0 h/w. Anuj: Add comments and commit message. Add gen 11 checks in the code. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Disable guardband clipping on SandyBridge for odd dimensionsvadym.shovkoplias2018-07-271-0/+11
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104388 Signed-off-by: Andriy Khulap <[email protected]> Acked-by: Rafael Antognolli <[email protected]>
* i965: Combine both gl_PatchVerticesIn lowering passes.Kenneth Graunke2018-07-262-51/+18
| | | | | | | | | | | | | | | | | | Until now, we had separate passes for lowering gl_PatchVerticesIn to a statically known constant (for TES inputs when linked against a TCS), and a uniform in the other cases. Annoyingly, one had to be run before nir_lower_system_values, and the other afterward. This simplified the passes, but made life painful for the callers. This patch combines both into a single pass. If you give it a non-zero static count, it uses that. If you give it Mesa state slots, it turns it back into a built-in uniform. Otherwise, it does nothing. This also moves the i965 uniform lowering out to shared code. v2: Make token arrays const. Reviewed-by: Eric Anholt <[email protected]>
* i965: Expose EXT_base_instance extension in OpenGLES 3.0Sagar Ghuge2018-07-261-1/+1
| | | | | | | | | | | | | | The extension requires at least OpenGL 3.0 and OpenGL ES 3.0. Fixes two ext_base_instance tests: arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3 arb_base_instance-drawarrays_gles3 Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965, anv: Use INTEL_DEBUG for disk_cache driver flagsJordan Justen2018-07-241-1/+2
| | | | | | | | | | | | | | | | | | | Since various options within INTEL_DEBUG could impact code generation, we need to set the disk cache driver_flags parameter based on the INTEL_DEBUG flags in use. An example that will affect the program generated by i965 is the INTEL_DEBUG=nocompact option. The DEBUG_DISK_CACHE_MASK value is added to mask the settings of INTEL_DEBUG that can affect program generation. v2: * Use driver_flags (Tim) * Also update Anvil (Jason) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965, anv: Add extra unused character in disk_cache renderer temp stringJordan Justen2018-07-241-2/+3
| | | | | | | | | | | | This extra character should not be used by snprintf, but we make it available to verify that we printed the exact number we wanted, and didn't overflow. v2: * Also update Anvil Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* python: Better iterate over dictionariesMathieu Bridon2018-07-241-2/+2
| | | | | | | | | | | | | | | | In Python 2, dictionaries have 2 sets of methods to iterate over their keys and values: keys()/values()/items() and iterkeys()/itervalues()/iteritems(). The former return lists while the latter return iterators. Python 3 dropped the method which return lists, and renamed the methods returning iterators to keys()/values()/items(). Using those names makes the scripts compatible with both Python 2 and 3. Signed-off-by: Mathieu Bridon <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* intel/compiler: Account for built-in uniforms in analyze_ubo_rangesJason Ekstrand2018-07-235-5/+5
| | | | | | | | | | | | The original pass only looked for load_uniform intrinsics but there are a number of other places that could end up loading a push constant. One obvious omission was images which always implicitly use a push constant. Legacy VS clip planes also get pushed into the shader. This fixes some new Vulkan CTS tests that test random combinations of bindings and, in particular, test lots of UBOs and images together. Cc: [email protected] Cc: Kenneth Graunke <[email protected]>
* i965/misc: Use depth/stencil surf's tiling on gen4-5Nanley Chery2018-07-191-1/+3
| | | | | | | | | | | | | Make the 3D engine aware of the depth/stencil surface's tiling before doing any render operations. Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e ("i965/miptree: Share tiling_flags in miptree_create"). Reported-by: Mark Janes <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248 Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Take an explicit filter parameter in blorp_blitJason Ekstrand2018-07-181-2/+61
| | | | | | | | This lets us move the glBlitFramebuffer nonsense into the GL driver and make the usage of BLORP mutch more explicit and obvious as to what it's doing. Reviewed-by: Chad Versace <[email protected]>
* i965: Sweep NIR after linking phase to free held memoryDanylo Piliaiev2018-07-181-0/+2
| | | | | | | | | | | | | | | | | | | After optimization passes and many trasfromations most of memory NIR holds is a garbage which was being freed only after shader deletion. Freeing it at the end of linking will save memory which would be useful in case there are a lot of complex shaders being compiled. The common case for this issue is 32bit game running under Wine. The cost of the optimization is around ~3-5% of compilation speed with complex shaders. V2: by Jason Ekstrand - Move nir_sweep up, right after the last change of NIR Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103274 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected]
* intel/blorp: fix uninitialized variable warningCaio Marcelo de Oliveira Filho2018-07-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Compiler doesn't pick up that level and start_layer will be defined, so do as was done for num_layers in 4d8b476fa9a "intel/blorp: Fix compiler warning about num_layers." and always set it. Fixes warning ../../src/mesa/drivers/dri/i965/brw_blorp.c: In function ‘brw_blorp_clear_depth_stencil’: ../../src/mesa/drivers/dri/i965/brw_blorp.c:1439:4: warning: ‘start_layer’ may be used uninitialized in this function [-Wmaybe-uninitialized] blorp_clear_depth_stencil(&batch, &depth_surf, &stencil_surf, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ level, start_layer, num_layers, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ x0, y0, x1, y1, ~~~~~~~~~~~~~~~ (mask & BUFFER_BIT_DEPTH), ctx->Depth.Clear, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ stencil_mask, ctx->Stencil.Clear); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../../src/mesa/drivers/dri/i965/brw_blorp.c:1439:4: warning: ‘level’ may be used uninitialized in this function [-Wmaybe-uninitialized] Reviewed-by: Anuj Phogat <[email protected]>
* i965/miptree: avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho2018-07-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | GCC 8.1.1 is having a hard time identifying that the values are properly initialized when used. In the 'memset_value' case, we pass the uninitialized value to another function (that will use only if the conditions match the initialization). Just give enough hint to the compiler to figure things out. Fixes the warnings ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function ‘intel_miptree_alloc_aux’: ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1839:18: warning: ‘memset_value’ may be used uninitialized in this function [-Wmaybe-uninitialized] mt->aux_buf = intel_alloc_aux_buffer(brw, &aux_surf, needs_memset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ memset_value); ~~~~~~~~~~~~~ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1698:10: warning: ‘initial_state’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (wants_memset) ^ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1772:23: note: ‘initial_state’ was declared here enum isl_aux_state initial_state; ^~~~~~~~~~~~~ Reviewed-by: Anuj Phogat <[email protected]>
* i965: batchbuffer: write correct canonical offset with softpinLionel Landwerlin2018-07-181-1/+2
| | | | | | | | | | | | | Addresses in the command streams should be in canonical form (i.e bit[63:48] == bit[47]). If the [bo->gtt_offset, bo->gtt_offset + target_offset] range contains the address 0x800000000000, the current code will fail that criteria. v2: Fix missing include (Lionel) Fixes: 1c9053d0765dc6 ("i965: Prepare batchbuffer module for softpin support.") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-6/+6
| | | | | | | | | | | | | | SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Allocate MS texture BOs as BUSYNanley Chery2018-07-131-2/+2
| | | | | | These buffer objects are never accessed with the CPU. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Inline make_separate_stencilNanley Chery2018-07-131-23/+6
| | | | | | | | | | Note that the separate stencil miptree now has the same alloc_flag as the depth component. Only stencil renderbuffers (as opposed to textures) have BO_ALLOC_BUSY. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Init r8stencil_needs_update to falseNanley Chery2018-07-131-3/+4
| | | | | | | | | | | | | | | The current behavior masked two bugs where the flag was not set to true after modifying the stencil texture. One case was a regression introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd and another was a bug in the depthstencil mapping code. These have since been fixed. To prevent such bugs from being masked in the future, initialize r8stencil_needs_update to false. v2: Keep the delayed allocation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Refactor miptree_createNanley Chery2018-07-131-36/+12
| | | | | | | | Enable a future patch to create the r8stencil_mt in this function. v2: Explicitly set etc_format to MESA_FORMAT_NONE (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add and use mt_surf_usageNanley Chery2018-07-131-13/+25
| | | | | | v2: Make mt_fmt const (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share alloc_flags in miptree_createNanley Chery2018-07-131-7/+4
| | | | | | | | | Note that this maintains BO_ALLOC_BUSY for depth renderbuffers, but not depth textures. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share the miptree format in miptree_createNanley Chery2018-07-131-15/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share tiling_flags in miptree_createNanley Chery2018-07-131-8/+7
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Delete MIPTREE_CREATE_LINEARNanley Chery2018-07-132-13/+3
| | | | | | | | | This enum constant was introduced to enable blit maps with intel_miptree_create da2880bea05bfc87109477ab026a7f5401fc8f0c. Now that such maps use the more direct make_surface function which allows you to specify the tiling directly, the constant is no longer being used. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use make_surface in map_blitNanley Chery2018-07-131-6/+6
| | | | | | | Do this so that we don't have to special case linearly-tiled depth buffers in miptree_create. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/draw: Fix adding the stencil bo to the depth cacheNanley Chery2018-07-131-1/+1
| | | | | | | | | Fix the case where stencil writes are enabled on a depth stencil texture. Found by inspection. v2: Fix message to allow for depth stencil writes (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/draw: Set the r8stencil flag after drawingNanley Chery2018-07-131-1/+11
| | | | | | | | | | | | | | Fixes the regresion introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd "i965: Use ISL for emitting depth/stencil/hiz state on gen6+" Found by inspection. Prevents regressing the piglit test, fbo-depth-array stencil-draw, later on in this series. Cc: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Set the r8stencil flag in map_depthstencilNanley Chery2018-07-131-1/+3
| | | | | | | | | | | Found by initializing the r8stencil_needs_update to false in make_separate_stencil_surface. Prevents regressing the piglit test arb_stencil_texturing-draw, later on in the series. Cc: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Set the r8stencil flag in miptree_finish_writeNanley Chery2018-07-134-17/+4
| | | | | | This seems to be the most appropriate place. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use the correct BLT pitchNanley Chery2018-07-121-6/+6
| | | | | | | | | | Retile miptrees to a linear tiling less often. Retiling can cause issues with imported BOs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738 Suggested-by: Chris Wilson <[email protected]> Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965/miptree: Drop an if case from retile_as_linearNanley Chery2018-07-121-4/+0
| | | | | | | | | | | Drop an if statement whose predicate never evaluates to true. row_pitch belongs to a surface with non-linear tiling. According to isl_calc_tiled_min_row_pitch, the pitch is a multiple of the tile width. By looking at isl_tiling_get_info, we see that non-linear tilings have widths greater than or equal to 128B. Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
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