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* i965: Upload state on primitive switch, don't just prepare it.Eric Anholt2008-11-121-0/+1
| | | | | This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke blender, among other apps.
* i965: Fix VB refcount leak on aperture overflow.Eric Anholt2008-11-121-0/+1
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* i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt2008-11-121-2/+14
| | | | | | As far as I can read in the docs, VS threads can be 1:1 with the pairs of VUE handles allocated for them. Also, G4X can run twice as many threads as before (though we won't unless the we bump the preferred URB entries for VS).
* i965: Fix up SF max_threads.Eric Anholt2008-11-121-1/+2
| | | | | | We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
* i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt2008-11-122-2/+16
| | | | | | | | | The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
* i965: Update WM maximum threads for G4X.Eric Anholt2008-11-121-2/+7
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* i965: Add a big comment explaining my understanding of URB management.Eric Anholt2008-11-121-1/+38
| | | | | It shouldn't offer anything new over what's in the docs (except for G4X notes), but here it's all in one place.
* mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul2008-11-061-4/+4
| | | | Trunc is a more accurate description; there's no type conversion involved.
* i965: Always check vertex program.Xiang, Haihao2008-11-061-1/+4
| | | | | | Now i965 also uses the vertex program created by Mesa Core, but this vertex program is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex program is updated or not. This fixes broken demo cubemap.
* i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong2008-11-052-10/+335
| | | | OPCODE_NOISE4 coming later.
* i965: Clean up stale NDC comment.Eric Anholt2008-11-021-2/+1
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* i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt2008-11-021-3/+3
| | | | This cuts one MOV out when setting a zero header.
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-028-22/+21
| | | | | The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
* i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt2008-11-021-3/+7
| | | | Also, add a comment explaining what brw->urb.constrained tries to do.
* Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard2008-11-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <[email protected]>
* i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-312-3/+405
| | | | (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
* i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-312-3/+3
| | | | This is required for scatter writes in destination regions to work.
* i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt2008-10-289-81/+133
| | | | | | | | Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive.
* intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt2008-10-284-13/+39
| | | | | | | This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
* i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong2008-10-282-3/+7
| | | | | This is required for threads to be spawned with correctly sized GRF register blocks.
* i965: Fix compiler warning from unused var.Eric Anholt2008-10-271-1/+0
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* i965: Remove dead brw->wrap flag.Eric Anholt2008-10-273-6/+0
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* i965: don't emit state when dri_bufmgr_check_aperture_space fails.Xiang, Haihao2008-10-242-4/+12
| | | | This ensures there is an unfilled batchbuffer used for emitting states again. Partial fix for #17964.
* i965: Add missing intel_pixel_draw.c symlink to fix build.Eric Anholt2008-10-101-0/+1
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* i965: Accelerate depth textures with border color.Eric Anholt2008-10-092-6/+20
| | | | | The fallback was introduced to fix bug #16697, but made the test it was fixing run excessively long.
* i965: Actually hook up the accelerated DrawPixels support.Eric Anholt2008-10-091-1/+2
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* i965: Add ARB_occlusion_query support.Eric Anholt2008-10-077-3/+310
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* i965: Fix a potential assertion failure.Xiang, Haihao2008-10-081-2/+4
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* i965: sampler default color ends up in texture cache, not instructions.Eric Anholt2008-10-011-1/+1
| | | | See volume 4, SAMPLER_BORDER_COLOR_STATE programming notes.
* i965: Fix overwriting of depth override for SetTexOffset.Eric Anholt2008-10-011-1/+0
| | | | Fixes black borders around windows in compiz. Bug #17233.
* Remove TNL-to-VP tracking from i965Ian Romanick2008-09-287-1665/+2
| | | | | | | | The i965 driver previously had it's own set of code to convert fixed-function TNL state to a vertex program. Core Mesa has code to do this, so there is no reason to duplicate that effort in the driver. In fact, this duplication leads to bugs when other aspects of the Mesa infrastructure change.
* intel: Fix a number of memory leaks on context destroy.Eric Anholt2008-09-263-2/+47
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* i965: support for sin() and cos() in vertex shaders.Sam Hocevar2008-09-251-0/+6
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* i965: more meaningful message for unsupported opcodes.Sam Hocevar2008-09-252-3/+8
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* i965: Cope with batch getting flushed in the middle of batchbuffer emits.Eric Anholt2008-09-235-12/+14
| | | | | | | | | This isn't required for GEM (at least, yet), but the check_aperture code for non-GEM results in batch getting flushed during emit. brw_state_upload restarts state emits, but a bunch of the state emit functions were assuming that they would be called exactly once, after prepare and before new_batch. Bug #17179.
* i965: Adapt to new TNL program tracking semanticsIan Romanick2008-09-221-1/+2
| | | | This fixes bugzilla #17718.
* i965: fix compilationBenjamin Close2008-09-221-2/+3
| | | | Found By: Tinderbox
* mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul2008-09-1842-114/+117
| | | | Makefile.template
* intel: track move of bo_exec from drivers to bufmgr.Eric Anholt2008-09-105-5/+0
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* intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt2008-09-1011-73/+72
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* intel: Fix depth_stencil texture.Xiang, Haihao2008-09-041-1/+1
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* intel: Fix refcounting on depth buffer initialization in DRI2.Eric Anholt2008-09-031-15/+3
| | | | (Reverts a change to work around the problem on 965).
* DRI2: Drop sarea, implement swap buffers in the X server.Kristian Høgsberg2008-08-291-3/+15
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* i965: force thread switch after IF/ELSE/ENDIF. partial fix for #16882.Xiang, Haihao2008-08-291-0/+5
| | | | | | A thread switch is implicitly invoked after the issuance of an IF/ELSE/ENDIF instruction if necessary. Unfortunately it seems sometimes a forced thread switch is needed.
* i965: mask control for BREAK/CONT/DO/WHILE. partial fix fox #16882Xiang, Haihao2008-08-291-4/+4
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* i965: Push/pop instruction state. partial fix for #16882Xiang, Haihao2008-08-291-2/+2
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* Revert "Revert "Merge branch 'drm-gem'""Dave Airlie2008-08-2430-514/+317
| | | | This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
* Revert "Merge branch 'drm-gem'"Dave Airlie2008-08-2430-317/+514
| | | | | | | | This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
* 965: Fix incorrect backface cullingKrzysztof Czurylo2008-08-214-15/+29
| | | | | Fix incorrect backface culling for OGL tunnel in wireframe and point mode.
* 965: Fix color clamping issuesKrzysztof Czurylo2008-08-211-0/+21
| | | | Patch is correctly applied this time.
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