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* mesa: Update vertex texture code after gallium changes.Michal Krol2009-12-011-0/+1
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* Merge commit 'origin/mesa_7_7_branch'Maciej Cencora2009-11-234-5/+11
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| * i965: Fix several memory leaks on exit.Eric Anholt2009-11-214-5/+11
| | | | | | | | Bug #25194.
* | intel: Remove non-GEM support.Eric Anholt2009-11-191-8/+0
| | | | | | | | | | This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked.
* | intel: Consistently use no_batch_wrap in intel_context struct.Eric Anholt2009-11-193-6/+2
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* | i965: Pack brw_wm_fragment_program better.Eric Anholt2009-11-191-1/+1
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* | mesa: Remove gratuitous padding in prog_dst_register.Eric Anholt2009-11-191-1/+0
| | | | | | | | | | | | | | The padding was there to indicate the amount of space left from the number of expected bytes in the struct minus allocated bits. But uint bitfields get packed so that they don't cross uint boundaries, and we ended up allocating an extra dword to hold the pad field!
* | i965: Pack the brw_wm_prog_key better.Eric Anholt2009-11-191-1/+1
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* Merge branch 'outputswritten64'Ian Romanick2009-11-1717-36/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h
* i965: Use MESA_FORMAT_AL1616 when appropriateIan Romanick2009-11-161-0/+3
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* i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-133-101/+63
| | | | This should fix TXB on G45 and older in the GLSL case.
* i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt2009-11-133-118/+72
| | | | | New comments should explain some of the confusion about how this message works.
* i965: Clean up emit_tex a bit.Eric Anholt2009-11-131-27/+24
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* Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt2009-11-1310-46/+81
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| * i965: Fix Ironlake shadow comparisons.Eric Anholt2009-11-121-7/+17
| | | | | | | | The cube map array index arg is always present.
| * i965: Fix VBO last-valid-offset setup on Ironlake.Eric Anholt2009-11-121-10/+3
| | | | | | | | | | Instead of doing math based on the (broken for VBO && offset != 0) input->count number, just use the BO size. Fixes assertion failure in ETQW.
| * i965: fix EXT_provoking_vertex supportRoland Scheidegger2009-11-118-29/+61
| | | | | | | | | | | | | | | | This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage.
* | i965: Flag BRW_NEW_CONTEXT on some context state.Eric Anholt2009-11-132-6/+6
| | | | | | | | | | | | Fixing this is a prereq for avoiding flagging all state at new batch time. Eliminating that still causes problems, though (notably glean logicOp fails on my GM965).
* | i965: Remove an unused cache_item field.Eric Anholt2009-11-132-2/+0
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* | i965: Remove long dead structures for ffvertex_prog.c.Eric Anholt2009-11-131-17/+0
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* | i965: Use bo_map instead of subdata to upload the bits of constant buffer.Eric Anholt2009-11-131-2/+5
| | | | | | | | Saves CPU time, resulting in a 2.5% FPS win on ETQW.
* | i965: Validate the number of URB entries selected for the VS.Eric Anholt2009-11-131-4/+33
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* | i965: Clean up Ironlake sampler type definitions.Eric Anholt2009-11-133-18/+10
| | | | | | | | They're the same regardless of execution width for 8, 4x2, and 16.
* | i965: Avoid moving the current value back into the accumulator for MAD.Eric Anholt2009-11-131-1/+34
| | | | | | | | | | This is a 2.9% (+/-.3%) performance win for my GL demo, which hits MAD sequences for matrix transforms.
* | Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt2009-11-101-1/+11
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| * i965: Fix VS constant buffer value loading.Eric Anholt2009-11-101-1/+11
| | | | | | | | | | | | | | | | | | | | Previously, we'd load linearly from ParameterValues[0] for the constants, though ParameterValues[1] may not equal ParameterValues[0] + 4. Additionally, the STATE_VAL type paramters didn't get updated. Fixes piglit vp-constant-array-huge.vpfp and ET:QW object locations. Bug #23226.
| * i965: Unalias src/dst registers for SGE and friends.Eric Anholt2009-11-101-19/+21
| | | | | | | | | | | | | | Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 (cherry picked from commit 56ab92bad8f1d05bc22b8a8471d5aeb663f220de)
| * i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt2009-11-101-1/+1
| | | | | | | | | | Fixes piglit arl.vp. (cherry picked from commit d52d78b4bcd6d4c0578f972c0b8ebac09e632196)
| * i965: be clear that the Fallback field is a boolean, not a bitfieldBrian Paul2009-10-273-4/+8
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| * Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()"Brian Paul2009-10-272-6/+2
| | | | | | | | | | | | | | | | | | This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c. It turns out the i965 driver uses the intel->Fallback field as a boolean, not as a bitmask. The intelFallback() function is a no-op in the i965 driver. It would have been nice if there were some comments about this. I'll fix that next...
* | i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.Eric Anholt2009-11-104-4/+23
| | | | | | | | | | | | | | | | | | For an app that's blowing out the state cache, like sauerbraten, the memset of the giant arrays ended up taking 11% of the CPU even when only a "few" of the entries got used. With this, the WM program compile drops back down to 1% of CPU time. Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
* | i965: Add a note explaining the data cache domain.Eric Anholt2009-11-101-1/+4
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* | i965: Unalias src/dst registers for SGE and friends.Eric Anholt2009-11-101-19/+21
| | | | | | | | | | | | Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228
* | i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt2009-11-101-1/+1
| | | | | | | | Fixes piglit arl.vp.
* | i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt2009-11-063-17/+29
| | | | | | | | | | | | | | No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
* | i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-063-60/+72
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* | i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-064-127/+40
| | | | | | | | This should fix issues with antialiased lines in GLSL.
* | i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-297/+109
| | | | | | | | | | The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
* | i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-221/+111
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* | i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-74/+29
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* | i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-30/+13
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* | i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-99/+33
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* | i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-063-45/+71
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* | i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt2009-11-062-34/+2
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* | i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-063-117/+38
| | | | | | | | | | This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
* | i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-062-7/+17
| | | | | | | | | | | | | | | | This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
* | i965: Always pass the size argument to brw_cache_data.Eric Anholt2009-11-066-57/+21
| | | | | | | | | | This keeps the individual state files from having to export their structures for brw_state_cache initialization.
* | i965: Remove an XXX comment for testing some code that seems to work.Eric Anholt2009-11-061-1/+0
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* | intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt2009-11-062-21/+2
| | | | | | | | | | | | This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary.
* | intel: avoid unnecessary front buffer flushing/updatingBrian Paul2009-11-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | Before, if we just called glXMakeCurrent() and didn't render anything we'd still trigger a flushFrontBuffer() call. Now only set the intel->front_buffer_dirty field at state validation time just before we draw something. NOTE: additional calls to intel_check_front_buffer_rendering() might be needed if I missed some rendering paths.
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