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path: root/src/mesa/drivers/dri/i965
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* i965: Use macros to create prototypes for emitter helpers.Kenneth Graunke2014-11-131-57/+41
* i965: Always enable VF statisticsBen Widawsky2014-11-131-2/+1
* i965/cfg: Remove if_block/else_block.Matt Turner2014-11-113-30/+1
* i965/fs: Don't use if_block/else_block in SEL peephole.Matt Turner2014-11-111-6/+11
* i965: Advertise a line width of 40.0 on Cherryview and Skylake.Kenneth Graunke2014-11-081-1/+5
* i965: Advertise larger line widths.Kenneth Graunke2014-11-081-3/+9
* i965: Use ctx->Const.MaxLineWidth when clamping ctx->Line.Width.Kenneth Graunke2014-11-084-5/+8
* i965: Set Line Width correctly on Cherryview and Skylake.Kenneth Graunke2014-11-082-1/+6
* i965: drop the custom gen8_instruction CFLAGEmil Velikov2014-11-071-2/+0
* i965/fs: Wire up control flow correctly in predicated break pass.Matt Turner2014-11-061-3/+7
* i965/cfg: Add functions to get first and last non-CF instructions.Matt Turner2014-11-061-0/+74
* i965: Remove non-existent vertical strides from array.Matt Turner2014-11-061-1/+1
* i965: Convert stride/width/execution size macros into enums.Matt Turner2014-11-061-28/+33
* i965/fs: Remove force uncompressed stack.Matt Turner2014-11-063-27/+0
* i965/fs: Use execution size of 1 for some shader_time operations.Matt Turner2014-11-061-1/+1
* i965/fs: Use mov(4) instructions to read timestamp.Matt Turner2014-11-061-5/+4
* i965: Fix sampler state pointer adjustment for nonconst samplersChris Forbes2014-11-051-1/+1
* i965: Re-enable Z16 on Gen8+.Kenneth Graunke2014-11-041-0/+7
* i965: Implement the PMA stall fix.Kenneth Graunke2014-11-044-0/+180
* i965: Add #defines for Broadwell HiZ workarounds in CACHE_MODE_1.Kenneth Graunke2014-11-041-0/+6
* i965: Update compaction code to handle Skylake like Cherryview.Kenneth Graunke2014-11-031-4/+4
* i965: Disable fast color clears on Skylake for now.Kenneth Graunke2014-11-031-1/+1
* i965/skl: Use new MOCS for SKLKristian Høgsberg2014-11-036-17/+33
* i965/skl: Implement workaround for VF Invalidate issueJordan Justen2014-11-031-0/+9
* i965/skl: Update Viewport Z Clip Test Enable bits for Skylake.Kenneth Graunke2014-11-032-2/+10
* i965/skl: Emit extra zeros in 3DSTATE_DS on Skylake.Kenneth Graunke2014-11-031-10/+5
* i965/skl: Init instructions compaction tables for SKLKristian Høgsberg2014-11-031-0/+1
* i965/skl: Add fast clear resolve rect multipliers for SKLKristian Høgsberg2014-11-031-2/+5
* i965/skl: Always emit 3DSTATE_BINDING_TABLE_POINTERS_* on Skylake.Kenneth Graunke2014-11-031-1/+1
* i965/skl: Allocate 16 DWords for SURFACE_STATE on Skylake.Kenneth Graunke2014-11-031-1/+1
* i965/skl: Refactor surface state allocation.Kenneth Graunke2014-11-031-10/+16
* i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake.Kenneth Graunke2014-11-031-2/+11
* i965/skl: Update stencil reference handling for Skylake.Kenneth Graunke2014-11-033-6/+28
* i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.Kenneth Graunke2014-11-031-1/+1
* i965/skl: Set max OpenGL version the same as gen7/8Jordan Justen2014-11-031-0/+1
* i965/skl: Update 3DSTATE_SBE for Skylake.Damien Lespiau2014-11-032-2/+34
* i965/fs: Don't compute_to_mrf() on Gen >= 7.Matt Turner2014-11-031-0/+4
* i965/chv: Increase VS and GS thread countsBen Widawsky2014-11-021-2/+2
* Revert "i965/compaction: Disable compaction on SNB temporarily."Matt Turner2014-10-291-6/+0
* i965/vec4: Perform CSE on MAD instructions with final arguments switched.Matt Turner2014-10-291-1/+5
* i965/fs: Perform CSE on MAD instructions with final arguments switched.Matt Turner2014-10-291-1/+5
* i965: Rename brw_vec4_gs.[ch] to brw_gs.[ch].Kenneth Graunke2014-10-295-5/+4
* i965: Rename brw_gs{,_emit}.[ch] to brw_ff_gs{,_emit}.[ch].Kenneth Graunke2014-10-295-5/+5
* i965: Rename intel_bufferobj_* functions to match GL and DD hooks.Kenneth Graunke2014-10-291-65/+64
* i965/fs: Don't set dependency hints on instructions with spilled destinationsJason Ekstrand2014-10-271-0/+8
* i965/fs: Make scratch write instructions use the correct execution sizeJason Ekstrand2014-10-271-1/+1
* i965/fs: Use correct spill offsetsJason Ekstrand2014-10-271-6/+5
* i965: Use the spill destination for the message header on GEN >= 7Jason Ekstrand2014-10-271-6/+13
* i965/fs: Don't [un]spill multiple registers at a time in SIMD8 modeJason Ekstrand2014-10-271-2/+4
* i965/fs: Use instruction execution sizes when generating scratch reads/writesJason Ekstrand2014-10-271-4/+4
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