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path: root/src/mesa/drivers/dri/i965
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* i965/vec4: Plumb log_data through so the backend_shader field gets set.Kenneth Graunke2015-07-098-8/+18
* i965: Switch on shader stage in nir_setup_outputs().Kenneth Graunke2015-07-091-26/+33
* i965: Set brw->batch.emit only #ifdef DEBUG.Matt Turner2015-07-092-1/+3
* i965/hsw: Implement end of batch workaroundBen Widawsky2015-07-092-2/+29
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-086-37/+64
* i965: Query whether we have kernel support for the TIMESTAMP register onceChris Wilson2015-07-083-5/+25
* i965/vs: Fix matNxM vertex attributes where M != 4.Kenneth Graunke2015-07-071-4/+11
* i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.Francisco Jerez2015-07-071-7/+1
* i965/gen4-5: Program the execution size correctly for DO/WHILE instructions.Francisco Jerez2015-07-071-1/+1
* i965/gen4-5: Set ENDIF dst and src0 fields to the null register.Francisco Jerez2015-07-071-2/+2
* i965: Reserve more batch space to accomodate Gen6 perfmonitors.Kenneth Graunke2015-07-061-2/+2
* i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRANeil Roberts2015-07-064-0/+9
* i965/fs: Don't disable SIMD16 when using the pixel interpolatorNeil Roberts2015-07-031-8/+3
* i965: allocate at least 1 BLEND_STATE elementMike Stroyan2015-07-021-1/+1
* i965/gen9: use an unreserved surface alignment valueNanley Chery2015-07-011-4/+4
* i965/fs: Use the builder directly for the gen6 interpolation add(32)Jason Ekstrand2015-07-011-6/+5
* i965/fs: Relax fs_builder channel group assertion when force_writemask_all is...Francisco Jerez2015-07-013-7/+7
* i965/fs: Fix PIXEL_X/Y in regs_read()Jason Ekstrand2015-06-301-1/+1
* i965/fs: Remove the width field from fs_regJason Ekstrand2015-06-308-107/+30
* i965/fs_generator: Use inst->exec_size for determining hardware reg widthsJason Ekstrand2015-06-301-7/+7
* i965/fs: Use exec_size instead of dst.width for computing component sizeJason Ekstrand2015-06-305-8/+8
* i965/fs: Use the builder dispatch_width for computing register offsetsJason Ekstrand2015-06-301-1/+1
* i965/fs: Use the builder dispatch width instead of dst.width for pull constantsJason Ekstrand2015-06-301-4/+4
* i965/fs: Remove exec_size guessing from fs_inst::init()Jason Ekstrand2015-06-301-22/+0
* i965/fs_builder: Use the dispatch width for setting exec sizesJason Ekstrand2015-06-301-9/+11
* i965/fs: Use exec_size for determining regs read/written and partial writesJason Ekstrand2015-06-301-3/+3
* i965/fs: Remove fs_inst constructors that don't take an explicit exec_sizeJason Ekstrand2015-06-304-39/+8
* i965/fs: Make better use of the builder in shader_timeJason Ekstrand2015-06-301-6/+8
* i965/fs: Add a builder argument to offset()Jason Ekstrand2015-06-307-123/+132
* i965/fs: Move offset(fs_reg, unsigned) to brw_fs.hJason Ekstrand2015-06-302-21/+21
* i965/blorp: Explicitly set execution sizes for new'd instructionsJason Ekstrand2015-06-301-4/+5
* i965/fs: Set the builder group for emitting FB-write stencil/AA alphaJason Ekstrand2015-06-301-1/+1
* i965/fs: Explicitly set the exec_size on the add(32) in interpolation setupJason Ekstrand2015-06-301-4/+6
* i965/fs: Properly handle LOAD_PAYLOAD in fs_inst::regs_readJason Ekstrand2015-06-301-0/+5
* i965/fs: Report the right value in fs_inst::regs_read() for PIXEL_X/YJason Ekstrand2015-06-301-2/+9
* i965/fs: Fix fs_inst::regs_read() for uniform pull constant loadsJason Ekstrand2015-06-301-0/+6
* i965/fs: Actually set/use the mlen for gen7 uniform pull constant loadsJason Ekstrand2015-06-302-13/+15
* i965/fs: Use a switch statement in fs_inst::regs_read()Jason Ekstrand2015-06-301-22/+23
* i965/fs: emit constants only onceConnor Abbott2015-06-302-13/+16
* i965/fs: use SSA values directlyConnor Abbott2015-06-305-30/+52
* nir/from_ssa: add a flag to not convert everything from SSAConnor Abbott2015-06-301-1/+1
* i965: use EmitNoIndirectSampler for gen < 7Tapani Pälli2015-06-301-0/+4
* i965: Don't use GCC extension for ?: with only two operands.Kenneth Graunke2015-06-291-3/+5
* i965/skl: Extract the blit command setup in to a helperAnuj Phogat2015-06-291-32/+61
* i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()Anuj Phogat2015-06-294-63/+287
* i965/gen9: Allocate YF/YS tiled buffer objectsAnuj Phogat2015-06-291-3/+62
* i965: Make a helper function intel_miptree_can_use_tr_mode()Anuj Phogat2015-06-291-11/+19
* i965: Make a helper function intel_miptree_release_levels()Anuj Phogat2015-06-291-6/+12
* i965/gen9: Plugin the code for selecting YF/YS tiling on skl+Anuj Phogat2015-06-291-17/+79
* i965: Make a helper function intel_miptree_set_alignment()Anuj Phogat2015-06-291-7/+14
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