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path: root/src/mesa/drivers/dri/i965
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* i965: Prevent coverity warningRobert Foss2017-02-011-0/+1
* i965/fs: Fix nir_op_fsign of absolute value.Francisco Jerez2017-01-311-1/+8
* i965: Support the force_glsl_version driconf option.Kenneth Graunke2017-01-292-0/+4
* i965: Fix check for negative pitch in can_do_fast_copy_blit().Kenneth Graunke2017-01-291-6/+4
* i965: add assert to while_jumps_before_offset()Timothy Arceri2017-01-301-0/+1
* i965: fix up asserts in brw_inst_set_jip()Timothy Arceri2017-01-301-2/+2
* i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.Kenneth Graunke2017-01-271-0/+43
* i965/sync: Implement fences based on Linux sync_fileChad Versace2017-01-271-3/+159
* i965/sync: Rename brw_fence_insert()Chad Versace2017-01-271-3/+3
* i965/sync: Fail sync creation when batchbuffer flush failsChad Versace2017-01-271-6/+28
* i965/sync: Add brw_fence::typeChad Versace2017-01-271-32/+71
* i965: Add intel_batchbuffer_flush_fence()Chad Versace2017-01-272-12/+26
* i965: Add intel_screen::has_fence_fdChad Versace2017-01-272-1/+4
* i915, i965: automake: remove NA include directiveEmil Velikov2017-01-271-1/+0
* i965: automake: include builddir prior to srcdirEmil Velikov2017-01-271-3/+3
* i965: automake: correctly set MKDIR_GENEmil Velikov2017-01-271-0/+1
* i965/hiz/gen6: Stop setting false qpitchTopi Pohjolainen2017-01-271-1/+7
* i965/blorp/gen6: Remove dead code in hiz setupTopi Pohjolainen2017-01-271-9/+9
* i965/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-273-12/+6
* i965/blorp/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-271-6/+4
* i965/gen6: Remove check for stencil formatTopi Pohjolainen2017-01-271-14/+8
* i965: Remove check for hiz on earlier gens than SNBTopi Pohjolainen2017-01-272-22/+2
* i965/miptree: Remove redundant check for null textureTopi Pohjolainen2017-01-271-6/+1
* i965/miptree: Tell when brw_miptree_layout() failsTopi Pohjolainen2017-01-273-7/+10
* i965/meta: Remove unused brw_get_rb_for_slice()Topi Pohjolainen2017-01-272-49/+0
* i965: Make intelEmitCopyBlit not truncate large strides.Kenneth Graunke2017-01-262-11/+7
* i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.Kenneth Graunke2017-01-261-1/+1
* i965: Fix fast depth clears for surfaces with a dimension of 16384.Kenneth Graunke2017-01-251-0/+12
* i965/blorp: Use the correct ISL format for combined depth/stencilJason Ekstrand2017-01-241-0/+2
* i965/blorp: Add also depth and stencil buffers to render cacheTopi Pohjolainen2017-01-241-0/+4
* i965: Use UNUSED to silence unused variable (used in assert).Matt Turner2017-01-231-1/+1
* dri: allow 16bit R/GR images to be exported via drm buffersRainer Hochecker2017-01-231-0/+6
* mesa/glsl/i965: set and get tes layouts directly to and from shader_infoTimothy Arceri2017-01-231-3/+3
* mesa/glsl: set {clip,cull}_distance_array_size directly in gl_programTimothy Arceri2017-01-231-1/+1
* mesa: use gl_program for CurrentProgram rather than gl_shader_programTimothy Arceri2017-01-239-56/+31
* Revert "i965: Really don't emit Q or UQ moves on Gen < 8"Matt Turner2017-01-201-8/+0
* i965: Select DF type for 64-bit integers on Gen < 8.Matt Turner2017-01-204-10/+12
* i965: Enable ARB_gpu_shader_int64 on Gen8+Ian Romanick2017-01-202-0/+6
* i965: Split SIMD16 CMP of Q and UQ instructionsIan Romanick2017-01-201-14/+29
* i965: Enable 64-bit integer support for almost all unary and binary operationsIan Romanick2017-01-201-10/+0
* i965: Enable uploading 64-bit integer uniformsIan Romanick2017-01-201-1/+3
* i965: Add 64-bit integer support for conversions and bitcastsIan Romanick2017-01-202-5/+35
* i965: Enable emitting Q and UQ instructions in the fs backendIan Romanick2017-01-202-1/+12
* i965: Add support for constant evaluation on Q and UQ typesIan Romanick2017-01-202-7/+20
* i965: Return Q and UQ types for int64 and uint64Ian Romanick2017-01-201-4/+2
* i965: Really don't emit Q or UQ moves on Gen < 8Ian Romanick2017-01-201-0/+8
* i965: Avoid int64 warnings.Dave Airlie2017-01-201-0/+28
* i965: Avoid int64 induced warningsDave Airlie2017-01-203-0/+6
* i965: Validate "Special Cases for Byte Operations"Matt Turner2017-01-202-9/+150
* i965: Validate "Region Alignment Rules"Matt Turner2017-01-202-1/+697