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path: root/src/mesa/drivers/dri/i965
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* i965: Replace broken handling of dead code with an assert.Eric Anholt2011-01-141-10/+12
* i965: Add an invalidation of live intervals after register splitting.Eric Anholt2011-01-141-0/+1
* i965: fix fbo-srgb on i965.Dave Airlie2011-01-141-0/+5
* i965: Remove unnecessary headers.Vinson Lee2011-01-131-2/+0
* i965/fs: Do flat shading when appropriate.Eric Anholt2011-01-122-20/+42
* i965: Clarify when we need to (re-)calculate live intervals.Eric Anholt2011-01-123-5/+27
* i965/vs: When MOVing to produce ABS, strip negate of the operand.Eric Anholt2011-01-121-0/+1
* i965/fs: When producing ir_unop_abs of an operand, strip negate.Eric Anholt2011-01-121-0/+1
* i965: Tighten up the check for flow control interfering with coalescing.Eric Anholt2011-01-111-12/+26
* i965: Remove dead fallback for stencil _Enabled but no stencil buffer.Eric Anholt2011-01-111-8/+0
* i965: Use a new miptree to avoid software fallbacks due to drawing offset.Eric Anholt2011-01-101-28/+1
* Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."Eric Anholt2011-01-103-10/+15
* i965: Add #defines for HiZ and separate stencil buffer commands.Kenneth Graunke2011-01-101-0/+3
* i965: Add new HiZ related bits to WM_STATE.Kenneth Graunke2011-01-101-1/+8
* i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.Kenneth Graunke2011-01-103-22/+22
* i965: Remove unused #defines which only contain the sub-opcode.Kenneth Graunke2011-01-101-22/+0
* intel: Add a vtbl hook for determining if a format is renderable.Eric Anholt2011-01-073-1/+18
* i965: Avoid double-negation of immediate values in the VS.Eric Anholt2011-01-071-4/+3
* i965: Rename various gen6 #defines to match the documentation.Kenneth Graunke2011-01-0612-33/+33
* intel: Always allocate miptrees from level 0, not tObj->BaseLevel.Eric Anholt2011-01-053-15/+10
* intel: Clarify first_level/last_level vs baselevel/maxlevel by deletion.Eric Anholt2011-01-053-6/+5
* i965: Simplify the renderbuffer setup code.Eric Anholt2011-01-051-102/+93
* i965: Add support for SRGB DXT1 formats.Eric Anholt2011-01-042-1/+5
* i965: Use last vertex convention for quad provoking vertex on sandybridgeZhenyu Wang2011-01-041-0/+7
* i965: Correct comment for gen6 fb write control message settingZhenyu Wang2011-01-041-1/+3
* i965: Fix provoking vertex select in clip state for sandybridgeZhenyu Wang2011-01-041-1/+4
* i965: Do lowering of array indexing of a vector in the FS.Eric Anholt2010-12-281-0/+1
* i965: Fix regression in FS comparisons on original gen4 due to gen6 changes.Eric Anholt2010-12-282-4/+32
* i965: Factor out the ir comparision to BRW_CONDITIONAL_* code.Eric Anholt2010-12-281-80/+34
* i965: Fix occlusion query on sandybridgeZhenyu Wang2010-12-281-0/+6
* Revert "i965: upload multisample state for fragment program change"Zhenyu Wang2010-12-283-38/+25
* i965: don't spawn GS thread for LINELOOP on SandybridgeXiang, Haihao2010-12-271-1/+4
* i965: Flatten if-statements beyond depth 16 on pre-gen6.Kenneth Graunke2010-12-271-0/+10
* i965: use align1 access mode for instructions with execSize=1 in VSXiang, Haihao2010-12-241-0/+2
* i965: fix register region descriptionXiang, Haihao2010-12-241-1/+1
* i965: Remove unnecessary headers.Vinson Lee2010-12-231-2/+0
* i965: Keep around a copy of the VS constant surface dumping code.Eric Anholt2010-12-231-0/+9
* i965: Correct the dp_read message descriptor setup on g4x.Eric Anholt2010-12-233-1/+23
* i965: upload multisample state for fragment program changeZhenyu Wang2010-12-233-25/+38
* i965: explicit tell header present for fb write on sandybridgeZhenyu Wang2010-12-224-8/+8
* i965: Avoid using float type for raw moves, to work around SNB issue.Eric Anholt2010-12-212-4/+8
* i965: Set the alternative floating point mode on gen6 VS and WM.Eric Anholt2010-12-163-0/+8
* i965: Add support for using the BLT ring on gen6.Eric Anholt2010-12-133-5/+7
* i965: Improve the hacks for ARB_fp scalar^scalar POW on gen6.Eric Anholt2010-12-131-36/+17
* i965: Fix gl_FragCoord.z setup on gen6.Eric Anholt2010-12-131-2/+7
* i956: Fix the old FP path fragment position setup on gen6.Eric Anholt2010-12-131-18/+20
* i965: Fix ARL to work on gen6.Eric Anholt2010-12-131-1/+17
* i965: Put common info on converting MESA_FORMAT to BRW_FORMAT in a table.Eric Anholt2010-12-101-126/+42
* i965: support for two-sided lighting on SandybridgeXiang, Haihao2010-12-105-6/+72
* i965: Add support for gen6 reladdr VS constant loading.Eric Anholt2010-12-092-11/+17