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* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-191-1/+1
| | | | | | | | More than half of the stuff in intel_reg.h had nothing whatsoever to do with registers and really belongs in brw_defines.h anyway. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Enforce that height == 1 for 1-D array texturesJason Ekstrand2016-07-201-0/+2
| | | | | | | | | | | | | | | | | | | The GL API and mesa internals do this differently than we do. In GL, there is no depth parameter for 1-D arrays and height is used. In the i965 miptree code we do the sane thing and make height == 1 and use depth for number of slices. This makes for a mismatch every time we create a 1-D array texture from GL. Instead of actually solving this problem, we just said "1-D is hard, let's make sure it works no matter which way we pass the parameters" and called it a day. This commit fixes the one GL -> i965 transition point where we weren't already handling 1-D array textures to do the right thing and then replaces the magic fixup code with an assert that you're doing the right thing. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: "12.0 11.2 11.1" <[email protected]>
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-8/+0
| | | | | | | | Shouldn't cause any functional changes at this point, but we have forgotten to apply this workaround several times in the past, make sure it doesn't happen again. Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: intel_texture_barrier reimplementedAlejandro Piñeiro2016-07-011-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: GL44-CTS.texture_barrier_ARB.same-texel-rw-multipass On Haswell, Broadwell and Skylake (note that in order to execute that test, it is needed to override GL and GLSL versions). On gen6 this test was already working without this change. It keeps working after it. This commit replaces the call to brw_emit_mi_flush for gen6+ with two calls to brw_emit_pipe_control_flush: * The first one with RENDER_TARGET_FLUSH and CS_STALL set to initiate a render cache flush after any concurrent rendering completes and cause the CS to stop parsing commands until the render cache becomes coherent with memory. * The second one have TEXTURE_CACHE_INVALIDATE set (and no CS stall) to clean up any stale data from the sampler caches before rendering continues. Didn't touch gen4-5, basically because I don't have a way to test them. More info on commits: 0aa4f99f562a05880a779707cbcd46be459863bf 72473658c51d5e074ce219c1e6385a4cce29f467 Thanks to Curro to help to tracking this down, as the root case was a hw race condition. v2: use two calls to pipe_control_flush instead of a combination of gen7_emit_cs_stall_flush and brw_emit_mi_flush calls (Curro) v3: no need to const cache invalidation (Curro) Reviewed-by: Francisco Jerez <[email protected]>
* i965: add ARB_texture_barrier supportIlia Mirkin2015-09-231-0/+9
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-061-1/+1
| | | | | | | | | Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it needed to include no tiling at all, but the name MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid confusion by replacing "ALLOC" with "TILING" in the identifiers. Reviewed-by: Ben Widawsky <[email protected]>
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad v4: Use parens to get the order right from v3. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-161-1/+1
| | | | This reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]> (v2) Reviewed-by: Anuj Phogat <[email protected]> (v2) Reviewed-by: Chad Versace <[email protected]> (v2)
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-121-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I think pretty much everyone agrees that having more than a single bool as a function argument is bordering on a bad idea. What sucks about the current code is in several instances it's necessary to propagate these boolean selections down to lower layers of the code. This requires plumbing (mechanical, but still churn) pretty much all of the miptree functions each time. By introducing the flags paramater, it is possible to add miptree constraints very easily. The use of this, as is already the case, is sometimes we have some information at the time we create the miptree that needs to be known all the way at the lowest levels of the create/allocation, disable_aux_buffers is currently one such example. There will be another example coming up in a few patches. v2: Tab fix. (Ben) Long line fixes (Topi) Use anonymous enum instead of #define for layout flags (Chad) Use 'X != 0' instead of !!X (everyone except Chad) v3: Some non-trivial conflict resolution on top of Anuj's patches. Signed-off-by: Ben Widawsky <[email protected]> Cc: "Pohjolainen, Topi" <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-5/+5
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Change intel_miptree_create_for_bo() signatureChad Versace2015-04-131-1/+2
| | | | | | | | | | | Add parameter 'bool disable_aux_buffers'. This is a refactor patch. The patch changes no behavior because the new parameter is false in every call. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/tex: Don't create read-write textures with non-renderable formatsJason Ekstrand2015-01-281-0/+5
| | | | | | | | | I haven't actually seen this bug in the wild, but it's possible that someone could ask to do a S3TC PBO download or something. This protects us from accidentally creating a render target with a compressed or otherwise non-renderable format. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement SetTextureStorageForBufferObjectJason Ekstrand2015-01-221-0/+57
| | | | Reviewed-by: Neil Roberts <[email protected]>
* main: Changed _mesa_alloc_texture_storage to _mesa_AllocTextureStorage_sw.Laura Ekstrand2015-01-081-1/+1
| | | | | | | | | | | | | | In order to implement ARB_DIRECT_STATE_ACCESS, many GL API functions must now rely on a backend that both traditional and DSA functions can use. For instance, _mesa_TexStorage2D and _mesa_TextureStorage2D both call a backend function _mesa_texture_storage that takes a context and a texture object as arguments. The backend is named _mesa_texture_storage so that Meta can call it and avoid looking up the context and the texture object. However, backend names often look very close to the names of software fallbacks (ie. _mesa_alloc_texture_storage). For this reason, software fallbacks have been renamed for clarity to have the form _mesa_[Driver function name]_sw. Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix intel_miptree_map() signature to be more 64-bit safeChad Versace2014-12-221-2/+5
| | | | | | | | | | | | | | | | | This patch should diminish the likelihood of pointer arithmetic overflow bugs, like the one fixed by b69c7c5dac. Change the type of parameter 'out_stride' from int to ptrdiff_t. The logic is that if you call intel_miptree_map() and use the value of 'out_stride', then you must be doing pointer arithmetic on 'out_ptr'. Using ptrdiff_t instead of int should make a little bit harder to hit overflow bugs. As a side-effect, some function-scope variables needed to be retyped to avoid compilation errors. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-151-1/+2
| | | | | | | | | | | | | gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Handle miptree creation failure in intel_alloc_texture_storage()Juha-Pekka Heikkila2014-06-261-0/+3
| | | | | | | | Check intel_miptree_create() return value before using it as a pointer. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Adjust map/unmap code for MinLevel/MinLayerChris Forbes2014-04-101-3/+8
| | | | | | | | | | This allows core mesa's TexSubImage paths etc to work correctly with views which have nonzero MinLevel or MinLayer. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Add _Format to intel_texobj.Chris Forbes2014-04-101-0/+9
| | | | | | | | | | | This is the actual mesa_format to use. In non-view cases this is always the same as the mt's format. V4: Comment style Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Add driver hook for TextureViewChris Forbes2014-04-101-0/+41
| | | | | | | | | | | We need to wire the original texture's mt into the view. All the hard work of setting up an appropriate tree of gl_texture_image structures has already been done by core mesa. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-1/+1
| | | | | | | Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Add a real native TexStorage path.Eric Anholt2013-09-301-0/+63
| | | | | | | | | | | | We originally had a path just did the loop and called ctx->Driver.AllocTextureImageBuffer(), which I moved into Mesa core. But we can do better, avoiding incorrect miptree size guesses and later texture validations by just directly allocating the miptree and setting it to all the images. v2: drop debug printf. Reviewed-by: Chad Versace <[email protected]>
* mesa: default DEPTH_TEXTURE_MODE should be RED in the core profileMarek Olšák2013-07-301-1/+1
| | | | | | | Cc: [email protected] Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move intel_context::intelScreen to brw_context.Kenneth Graunke2013-07-091-2/+1
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke2013-07-091-5/+6
| | | | | | | | | | | | | | This makes brw_context available in every function that used intel_context. This makes it possible to start migrating fields from intel_context to brw_context. Surprisingly, this actually removes some code, as functions that use OUT_BATCH don't need to declare "intel"; they just use "brw." Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Replace #include "intel_context.h" with brw_context.h.Kenneth Graunke2013-07-091-1/+1
| | | | | | | | | | | brw_context.h includes intel_context.h, but additionally makes the brw_context structure available. Switching this allows us to start using brw_context in more places. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move the remaining intel code to the i965 directory.Eric Anholt2013-06-261-1/+189
| | | | | | | | | Now that i915's forked off, they don't need to live in a shared directory. Acked-by: Kenneth Graunke <[email protected]> Acked-by: Chad Versace <[email protected]> Acked-by: Adam Jackson <[email protected]> (and I hear second hand that idr is OK with it, too)
* [965] Move to using shared texture management code.Eric Anholt2007-12-161-316/+1
| | | | | | This removes the delayed texture upload optimization from 965, in exchange for bringing us closer to PBO support. It also disables SGIS_generate_mipmap, which didn't seem to be working before anyway, according to the lodbias demo.
* [965] Replace 965 texture format code with common code.Eric Anholt2007-11-201-0/+1
| | | | | The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+315
This driver comes from Tungsten Graphics, with a few further modifications by Intel.
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